TLE7241EXT Infineon Technologies, TLE7241EXT Datasheet
TLE7241EXT
Specifications of TLE7241EXT
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TLE7241EXT Summary of contents
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Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Dual Channel Constant Current Control Solenoid Driver 1 Overview 1.1 Features • Two Fully Independent Channels • Integrated N-channel DMOS transistors • Programmable Average Current with 10-bit resolution via SPI I – range = 0 to 1000 mA (typical) avg ...
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Applications • Variable force solenoids (e.g. automatic transmission solenoids) • Constant current controlled solenoids like – Idle Speed Control – Exhaust Gas Recirculation – Valve control – Suspension Control 1.3 General Description The TLE 7241E is a dual channel ...
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Application Block Diagram DEFAULT TEST VSO SI SO SPI SCK CSB Figure 1 Basic Application Diagram Data Sheet VDD BAT REF Logic Channel 1 BAT REF Channel 2 GND PGND2 5 TLE 7241E Overview VBAT VBAT OUT1 VBAT NEG1 POS1 ...
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Detailed Block Diagram REF 14 Int Register Vref Vcal detect Vref Fault type bit Dither Register VSO Average Current DEFAULT 7 Hysteresis TEST 13 Error Cor Reg Error Cor Reg VSO Error Cor Reg 11 Error Cor Reg Error Cor ...
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Pin Configuration Pin Assignment PGND1 OUT1 NEG1 POS1 N.C. VDD DEFAULT SCK CSB Figure 3 Pin-Out Pin Definitions and Functions Pin Pin Name 1 PGND1 2 OUT1 3 NEG1 4 POS1 DEFAULT Data ...
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Pin Definitions and Functions (cont’d) Pin Pin Name 8 SCK 9 CSB TEST 14 REF 15 GND 16 BAT 17 POS2 18 NEG2 19 OUT2 20 PGND2 Expose EPGND d Lead Frame ...
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Maximum Ratings Absolute Maximum Ratings T = -40 to 150 °C j Pos. Parameter Voltages M.1 Supply Voltage M.2 Analog Input Voltage M.3 Output Voltage M.4 Digital Input Voltage M.5 Digital Output Pin Voltage M.6 Dynamic Clamp Voltage T ...
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Absolute Maximum Ratings T = -40 to 150 °C j Pos. Parameter M.12 ESD HBM all pins EIA/JESD22-A 114B (1.5 K Ω, 100 pF) M.13 ESD MM all pins EIA/JESD22-A115A (0 Ω, 200 pF) 1) Not subject to production test, ...
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Functional Range Functional Range T = -40 to 150 ° 2.5V j REF Pos. Parameter F.1 Voltage at BAT V F.2 Voltage at DD F.3 Voltage at VSO F.4 Voltage at SI, SCK F.5 Voltage at CSB, ...
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Not subject to production test, specified by design. 2) Both channels on with 1W power dissipation per channel 3) Specified RthJA value is according to Jedec JESD51-2, - natural convection on FR4 2s2p board. The Product (Chip+Package) ...
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Functional Description and Electrical Characteristics Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at the given ...
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Input/Output The DEFAULT pin is an active high input. A weak pull-up current (typical 15 μA) on this pin ensures a defined level when this pin is not connected (e.g. open pin). An active high signal on the DEFAULT ...
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Power Output The slew rate of the voltage on the pins OUT1 and OUT2 are programmable via the SPI interface. The fast settings are intended for fast switching solenoids (low inductance) to minimize power dissipation within the TLE 7241E, ...
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Protection and Control Electrical Characteristics = -40 to 150 ° BAT Pos. Parameter Symbol 5.4.1 POS/NEG POS/NEG IBIAS IBIAS 5.4.2 POS/NEG POS/NEG LEAKAGE LEAKAGE 1) Positive current flow is ...
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V V POSx - NEGx on LS-Switch state off Vov Vov-ovhyst Vpwr 14 V Figure 4 Overvoltage Shutdown Electrical Characteristics T = -40 to 150 ° BAT Pos. Parameter 5.4.1.1 BAT ...
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Overcurrent / Short to latched until the fault register is read via SPI. The driver will remain in the off condition for the short circuit refresh time (see table below, the driver ...
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V V POSx - NEGx Vpos LS-Switch state Short to Load State VSHTx fault state VSHTx latched fault state CSB MOSI MISO V Figure 5 Short POSx - NEGx Vposx LS-Switchx state Short to Vbat Load State ...
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SHORT TO Vbat FAULT - OCCURS WHILE OFF THEN TURNED OSx - NEGx 15V Vpos 0V on LS-Switch state off Short to Vbat Load State VSHTx fault state VSHTx latched fault state CSB MOSI MISO V ...
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Open Load / Short to Ground Detection The OLSG fault bit is set under the following conditions. Operating Condition #1 The average current command is > (with 1 Ω sense resistor) and the low-side driver is ON ...
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Characteristics” on Page Characteristics” on Page pin when the Fault Typing bit = 1. Distinguishing between Open Load and Short to Ground Faults When an Open Load/Short to Ground is flagged, to distinguish between Open Load and Short-To-Ground, a ...
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Electrical Characteristics T = -40 to 150 ° BAT Pos. Parameter 5.4.3.1 POS Open detect current 5.4.3.2 POS Load short to ground detect 5.4.3.3 OUTx On-State open sense time – POS ...
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Diagnostics Timing Diagrams OPEN CIRCUIT / SHORT TO GROUND FAULT - OCCURS & CLEARS WHILE POS - NEG on Output transistor state off open Load State OL/SGx fault state OL/SGx latched fault state CSB MOSI MISO Figure ...
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V POSx 2.5V open Load State ok OL/SGx fault state OL/SGx latched fault state CSB MOSI MISO The Latched Fault State is sampled and stored in the SPI transmit register at the points marked with “ Figure 10 Open ...
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V POSx 2.5V open Load State ok OL/SGx fault state OL/SGx latched fault state CSB MOSI MISO Figure 11 Open Load / Short to Ground - Channel Off Then Turned On Data Sheet Functional Description and Electrical Characteristics OPEN ...
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OPEN CIRCUIT FAULT - OCCURS WHILE OFF THEN OPEN LOAD / SHORT TO GROUND 14V V POSx 2.5V open Load State ok OL/SGx fault state OL/SGx latched fault state CSB MOSI MISO The Latched Fault State is sampled and stored ...
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V POSx 2.5V t < tos Short to GND Load State ok OL/SGx fault state OL/SGx latched fault state CSB G.C. cmd MOSI G.C. response MISO OLSG=0 The Latched Fault State is sampled and stored in the SPI transmit ...
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OSx - NEGx LS-Switch x state OT shutdown Sensor temp x OT shutdown - OT hyst OTMPx fault state OTMPx latched fault state CSB MOSI MISO Figure 14 Overtemperature Shutdown with Restart Electrical Characteristics = -40 ...
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Current Control 5.5.1 Hysteretic Current Control The TLE 7241E device uses a hysteretic control method to regulate the solenoid current. The output transistor is toggled on and off based on the measured value of the solenoid current. The solenoid ...
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Note that the switching frequency and duty cycle of the output transistor are not directly controlled by the TLE 7241E device and are dependent on the characteristics of the solenoid (inductance, resistance, etc.) and the solenoid supply voltage. Electrical Characteristics ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter Symbol 4)5) 5.5.1.7 OUTx OUT 1000 mV I register avg = 340 H 3)5) 5.5.1.8 ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter Symbol 3)5) 5.5.1.11 OUTx d Switching hysteresis 70 Sw Hyst. register = 3 DAC counts = ±29 3)5) 5.5.1.12 ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter Symbol 3)5) 5.5.1.14 OUTx d Switching hysteresis 100 Sw Hyst. register = 6 DAC counts = ±42 3)5) 5.5.1.15 ...
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Figure 16 Blanking Time (output transistor turning off) Data Sheet Functional Description and Electrical Characteristics 35 TLE 7241E Rev. 1.1, 2009-01-19 ...
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Figure 17 Blanking Time (output transistor turning on) Data Sheet Functional Description and Electrical Characteristics 36 TLE 7241E Rev. 1.1, 2009-01-19 ...
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Dither Control and Operation The dither waveform is generated digitally within the TLE 7241E by periodically adding or subtracting from the average current command register contents. illustration of the Dither Waveform. Figure 18 Dither Waveform The Dither Frequency can ...
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Figure 19 Enhanced Dither Waveform When the enhanced dither bit is selected, the dither period will only be extended if the lower switch threshold is not crossed during the entire negative slope portion of the dither waveform. Example see Figure ...
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Figure 20 Enhanced Dither Waveform The extension of the dither period will be terminated when the lower switch threshold is crossed or when the extension time has exceeded the enhanced dither time out period (minimum 15 ms) - see Figure ...
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Enhanced Dither Time Out Figure 21 Enhanced Dither Time-out Data Sheet Functional Description and Electrical Characteristics 40 TLE 7241E Rev. 1.1, 2009-01-19 ...
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Electrical Characteristics T = -40 to 150 ° BAT Pos. Parameter 3) 5.5.2.1 OUTx Enhanced Dither time out 3)4) 5.5.2.2 OUTx Dither Amplitude Reg = 04 H 3)4) 5.5.2.3 OUTx Dither ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter 5.5.2.12 OUTx Dither Frequency Reg = 15 H 5.5.2.13 OUTx Dither Frequency Reg = 11 H 5.5.2.14 OUTx Dither ...
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Input Command Out of Range / Dither Clipping If an average current command between 000 a 1 Ω sense resistor) is received, then the average current will be set to 000 (channel disabled) and the COR (command out of ...
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Figure 22 Symmetrical Dither Clipping 5.5.4 Error Correction Registers / Average Switch Threshold Trimming The average switch threshold of each channel is trimmed at wafer test under the following operating conditions: average current command = 299 hysteresis = 80 mVpp. ...
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Error Correction Corresponding Average Register # Current Register Setting (Hex) 0 0A6 1 14D 2 1F3 3 29A 4 340 For example: • Measured average switch threshold at 0A6 • Ideal average switch threshold at 0A6 • Error Correction = ...
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SPI Command and Diagnosis Structure 5.6.1 SPI Signal Description The SPI serial interface has the following features: • Full duplex, 4-wire synchronous communication • Slave mode operation only • Fixed SCK polarity and phase requirements • Fixed 16-bit command ...
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Figure 23 SPI Timing Diagram Data Sheet Functional Description and Electrical Characteristics 47 TLE 7241E Rev. 1.1, 2009-01-19 ...
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Electrical Characteristics T = -40 to 150 ° BAT Pos. Parameter 5.6.1.1 CSB Input Bias Current 5.6.1.2 SI Input Pull- down Current 5.6.1.3 SCK Input Pull- down Current 5.6.1.4 SO Tri-state ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter 5.6.1.10 SO, CSB SO Pin Enable/ Disable 3) 5.6.1.11 SO, SCK Output Data Setup Time SCK Rising ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter 5.6.1.16 SI, CSB, SCK Serial Inputs Rise/Fall Time 5.6.1.17 CSB, SCK CSB Falling Edge to SCK Rising Edge 5.6.1.18 ...
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Electrical Characteristics (cont’ -40 to 150 ° BAT Pos. Parameter 5.6.1.23 SCK Number of SCK pulses while CSB low ( positive integer) 3) 5.6.1.24 CSB MISO shift ...
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SPI Command Structure Table 1 SPI Command Summary Channel Instruction ID Command Type B15 B14 B13 ...
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MISO • B12 Diagnostic Error OL/ VSHT = 1 or OTMP = 1 (channel specific) • B11 Command out of Range the average current set point + the hysteresis setting result ...
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Table 2 Average Output Current Key (typical) - Partial Table (cont’d) COR Hex Average 0 340 … 1) 3D3 3D4 ...
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B15 B14 B13 B12 MOSI MISO Figure 26 Dither Programming MOSI • B12 Enhanced Dither: Enables the enhanced dither feature when Default = 0 (disabled) • B11 - B7 ...
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Figure 27 Start of Dither Cycle Data Sheet Functional Description and Electrical Characteristics 56 TLE 7241E Rev. 1.1, 2009-01-19 ...
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Table 3 Ideal Dither Amplitude Key (typical) Hex DA4 DA3 DA2 DA1 DA0 Dither ...
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Table 3 Ideal Dither Amplitude Key (typical) Hex DA4 DA3 DA2 DA1 DA0 Dither register value 10.5 V ----------------------------------------------------- - ...
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Table 4 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) Hex DF6 DF5 DF4 ...
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Table 4 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) Hex DF6 DF5 DF4 ...
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Table 4 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) Hex DF6 DF5 DF4 ...
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Table 4 Ideal Dither Frequency Key (typical)- Partial Table (cont’d) Hex DF6 DF5 DF4 ...
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B15 B14 B13 B12 MOSI MISO OL/SG VSHT OTMP Figure 28 General Configuration Register MOSI • B12 - B6: Not used, Ignored - Don’t Care B5 Fault Typing Bit: Activates a 40 μA ...
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Table 5 Slew Rate Control Key SR1 SR0 Table 6 Switching Hysteresis Key SH2 SH1 B15 ...
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MISO • B12 - 11 Command Extension: Always 00 • B10 - B8 RID0-2: Register ID of the register contents • RV: Register contents Table 7 Error Register Values per Channel RID2 RID1 ...
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Application +5V +5V or 3.3V Rso (5) μController Rdft (1). Tri-Core TC17XX Figure 30 Application Circuit Note: This is a very simplified example of an application circuit. The function must be verified in the real application 1. Recommended for ...
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Layout Notes • The POS pin should be connected directly to the external sense resistor with a dedicated trace. • The NEG pin should be connected directly to the external sense resistor with a dedicated trace. • The POS ...
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Package Outlines 1.27 2) 0.4 ±0.08 0. Index Marking 12.8 -0.2 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per ...
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Revision History Version Date Rev. 1.1 2009-01-19 Page 68: Updated Package drawing (Stand-off) Data Sheet Changes Page 69-70: added Revision History, updated Legal Disclaimer 69 TLE 7241E Revision History Rev. 1.1, 2009-01-19 ...
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... Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life ...
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... Published by Infineon Technologies AG ...