ZT5515A-1BW Intel, ZT5515A-1BW Datasheet - Page 18

• Manufacturer Part Number: ZT5515A-1BW
• Manufacturer: Intel

Specifications of ZT5515A-1BW

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Introduction
2.3.17
2.3.18
2.3.19
2.3.20
2.3.21
18
The ZT 5515's Real-Time Clock resides in the Intel ICH4 device.
See
Reset
The push-button reset on the ZT 5515's faceplate functions as a “Hard Reset.”
See
Two-Stage Watchdog Timer
The watchdog timer optionally monitors system operation and is programmable for one of eight
different timeout periods (from 0.25 seconds to 256 seconds). It is a two-stage watchdog, meaning
that it can be enabled to produce a non-maskable interrupt (NMI) or a “CPU init” before it
generates a Reset. Failure to strobe the watchdog timer within the programmed time period may
result in an NMI, a reset request, or both. A register bit can be enabled to indicate if the watchdog
timer caused the reset event. This watchdog timer register is cleared on power-up, enabling system
software to take appropriate action if the watchdog generated the reboot.
See
Universal Serial Bus (USB)
The Universal Serial Bus (USB) provides a common interface to slower-speed peripherals.
Functions such as keyboard, serial ports, printer port, and mouse ports can be consolidated into
USB, simplifying cabling requirements. The ZT 5515 provides one USB port at its faceplate
(connector J20 is Port 0). USB Port 1 and USB port 2 are routed to the ZT 5515's J5 Rear Panel I/
O connector.
The ZT 5515’s USB channels are controlled by the Intel ICH4 device.
See
Baseboard Management Controller
The ZT 5515 includes an Intel Baseboard Management Controller (BMC) chip, the VT22030A
which interfaces to the LPC bus. The BMC provides SMBus (System Management Bus) interfaces
and is IPMI (Intelligent Platform Management Interface) compliant. The BMC subsystem
monitors, controls, and performs remote diagnostics for on- and off-board functions.
See
IDE Controller
Only the ZT 5515A-1B (and not the ZT 5515A-1A) features an ATA-100 IDE connector that
supports an onboard IDE drive. ATA-100, also called DMA-100, is an enhancement to earlier IDE
standards that increases throughput to 100 Mbytes/sec using Bus Master IDE transfers.
Intel
Section D.3, “Intel 845E Chipset” on page 83
Chapter 5, “Reset,”
Chapter 8, “Watchdog Timer,”
Section D.3, “Intel 845E Chipset” on page 83
Chapter 6, “System Monitoring and Control”
®
NetStructure
TM
for more information about reset sources for the ZT 5515.
ZT 5515 Compute Processor Board Technical Product Specification
for more information, including sample code.
for more details.
for a link to the datasheet for this device.
for a link to the datasheet for this device.