ZT5515A-1BW Intel, ZT5515A-1BW Datasheet - Page 82

• Manufacturer Part Number: ZT5515A-1BW
• Manufacturer: Intel

Specifications of ZT5515A-1BW

• Lead Free Status / Rohs Status: Supplier Unconfirmed

System Registers
C.1.7
82
Table 42. Geographic Addressing (E4h)
Table 43. SM Bus Enable (E6h)
SMBus Enable (E6h)
7:6
5
4:0
Address Offset:
Default Value:
Size:
Attribute:
7
6
5
4:0
Bit
Bit
Intel
Reserved
Ethernet Channel A Front/Rear panel Switching
This bit controls the MUX used to switch Ethernet channel A between the front and rear panel. A logical
0 selects the front panel. A logical 1 selects the rear panel. The power up default is 0. This is also a
BIOS selectable option.
Geographic Addressing
CompactPCI defines several signal additions to the PCI specification. One of these is GA[4..0], used
for geographic addressing on the backplane. Geographic addressing uniquely differentiates each
board based upon the physical slot into which it was inserted. Each backplane connector in a
CompactPCI system has a unique code for GA[4..0]. See the CompactPCI Specification, PICMG 2.0,
Version 2.1 for more information on geographic addressing. The bits correspond to signals as follows:
Bit 0 = GA0; Bit 1 = GA1; Bit 2 = GA2; Bit 3 = GA3; Bit 4 = GA4.
A logical 0 indicates that the corresponding GA pin is open. A logical 1 indicates that the corresponding
GA pin is low (GND).
Reserved
J1 SMBus Enable
This bit enables SMBus function through the rear panel J1 connector. A logical 1 enables this function.
Rear Panel NMI status
A 1 indicates that a NMI was asserted by the rear panel. Users can write a 0 to clear this bit.
RESERVED
®
NetStructure
TM
ZT 5515 Compute Processor Board Technical Product Specification
E6h
0x00
8 bits
R/W
Description
Description