ZT5515A-1BW Intel, ZT5515A-1BW Datasheet - Page 38

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ZT5515A-1BW

Manufacturer Part Number
ZT5515A-1BW
Description
Manufacturer
Intel
Datasheet

Specifications of ZT5515A-1BW

Lead Free Status / Rohs Status
Supplier Unconfirmed
System Monitoring and Control
6.1.1
6.1.2
6.2
38
Table 16. SMBus Device Details
Field Replaceable Unit (FRU) Information
The BMC controller will store the FRU information about the board and the rear panel cards. Each
device will have its own Address. This device is a 32K x 8 device used to hold information about
the card.
Host CPU controller = Device 0
Host CPU Rear Panel Card = Device 1
System Event Log Information
The BMC controller stores system event information in an 8K x 8 serial EEPROM device. Both the
in-band KCS interface and the out-of-band IPMB interface provide access to the System Event Log
(SEL). This allows SEL information to be accessed through the IPMB interface even if the system
is down.
SMBus Address Map
The table below lists the location, function, and address of each SMBus device used on the
ZT 5515.
ADM1026
Ethernet A
Ethernet B
FRU
SEL
DDR SDRAM
CK408
Intel
CPU board power on/power off control
CPU NMI Assertion to processor
Dual Domain Mode
Device
®
NetStructure
CPU voltage and temperature monitoring
Ethernet controller A
Ethernet controller B
Field Replaceable Unit SEEPROM
System Event Log SEEPROM
Signal Presence Detect (SPD) PROM
Clock generator
TM
ZT 5515 Compute Processor Board Technical Product Specification
ZT 5515 Function
0101100
0001000
0001001
1010011
1010 011
1010000
1101001
Address