TMC2249AH5C1 Fairchild Semiconductor, TMC2249AH5C1 Datasheet - Page 11

• Manufacturer Part Number: TMC2249AH5C1
• Manufacturer: Fairchild Semiconductor

Specifications of TMC2249AH5C1

• Function: Digital Mixer
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: MQFP
• Pin Count: 120
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

TMC2249A
Once all of the products of the desired taps have been
summed, the result is available at the output. The user then
"pushes" a new time-data sample on to the appropriate even
or odd data register "stack" and reiterates the summation.
Note that the coefficient bank "pointers", the BDEL and
DDEL delay words, are alternately incremented and decre-
mented on successive filter passes to maintain alignment
between the incoming data samples and their respective
coefficients.
The effective filter speed is calculated by dividing the clock
rate by one-half the number of taps implemented.
Alternatively, non-symmetric FIR filters can be implemented
using the TMC2249A in a similar fashion. Here, a shift reg-
ister is used to delay the incoming data fed to the A input by
an amount equal to one-half the length of the filter (the
length of the A delay register).
Table 4. FIR Filtering – Operation Sequence
Notes:
1. If only the 16 MSBs of the result are used, the user may leave RND HIGH and SWAP low. If the 16 LSBs or all 24 bits of the
2.
REV. 1.0.2 7/6/00
Cycle
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
•
•
result are used, then RND should be set low.
s
=
Push
A
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
K
15
=
0
B
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
x k h k
x(32)
Push
C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+
D
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
x k
ADEL
+
D
0
1
2
3
4
5
6
7
8
9
A
B
C
E
F
0
1
2
3
4
16
h k
CDEL
D
0
1
2
3
4
5
6
7
8
9
A
B
C
E
F
0
1
2
3
4
BDEL
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
E
D
C
B
F
F
DDEL
A
B
C
D
D
C
B
0
1
2
3
4
5
6
7
8
9
E
F
F
E
ACC
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
ENA
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
As shown in Figure 5, the data is then sent to the C input,
thus "stacking" the A and C delay registers to create a single
N-tap FIR filter. The incremented delay words (ADEL-
DDEL) for all four inputs are identical. Again, the filter
throughput is equal to the clock speed divided by one-half
the number of taps implemented.
Figure 5. Non-Symmetric 32-Tap FIR Filtering Using the
ENB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
x(m)
ENC
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
16-Stage Shift Register
END
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
x(m+15)
x(m+0)
TMC2011A
A
+x(21) h(10)+x(20) h(11)
+x(19) h(12)+x(18) h(13)
+x(17) h(14)+x(16) h(15)
+x(15) h(15)+x(14) h(14)
+x(13) h(13)+x(12) h(12)
+x(11) h(11)+x(10) h(10)
+x(29) h(2)+x(28) h(3)
+x(27) h(4)+x(26) h(5)
+x(25) h(6)+x(24) h(7)
+x(23) h(8)+x(22) h(9)
+x(31) h(1)+x(32) h(0)
+x(29) h(3)+x(30) h(2)
+x(27) h(5)+x(28) h(4)
+x(25) h(7)+x(26) h(6)
+x(23) h(9)+x(24) h(8)
x(31) h(0)+x(30) h(1)
+x(9) h(9)+x(8) h(8)
+x(7) h(7)+x(6) h(6)
+x(5) h(5)+x(4) h(4)
+x(3) h(3)+x(2) h(2)
+x(1) h(1)+x(0) h(0)
Convolutional Sum
TMC2249A
h(15)
h(0)
B
Filter Output
S
15-0
PRODUCT SPECIFICATION
x(m+16)
x(m+31)
C
TMC2249A
h(16)
h(31)
See Note 2
Resultant
D
Output
11