TMC2249AH5C1 Fairchild Semiconductor, TMC2249AH5C1 Datasheet - Page 6

• Manufacturer Part Number: TMC2249AH5C1
• Manufacturer: Fairchild Semiconductor

Specifications of TMC2249AH5C1

• Function: Digital Mixer
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Package Type: MQFP
• Pin Count: 120
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

PRODUCT SPECIFICATION
Pin Descriptions
6
Pin Name
Controls
ENA-END N13, N2, C12,
NEG1,2
RND
FT
CASEN
ACC
SWAP
OE
No Connect
CPGA/PPGA/
MPGA
B1, D3
D13
E11
L12
M1
A3
C2
B2
K3
D4
Pin Number
(continued)
60, 33, 89, 116 Input Enables. Input data presented to port i11-0 (i=A,B,C, or D)
MQFP
3, 4
84
83
28
27
65
5
2
Pin Function Description
are latched into delay pipeline i, and data already in pipeline i
advance by one register position, on each rising edge of CLK for
which ENi is LOW. When ENi is HIGH, the data in pipeline i do not
move and the value at the input port i will be lost before it reaches
the multiplier.
Negate. The products of the multipliers are negated causing a
subtraction to be performed during the internal summation of
products, when the NEGate controls are HIGH, NEG1 negates the
product A x B, while NEG2 acts on the output of the multiplier which
generates the product C x D. When the length controls ADEL–
DDEL are set to zero, these controls indicate the operation to be
performed on data input during the same clock. As nonzero values
for ADEL–DDEL do not affect the pipelining of these controls, their
effect is not synchronous with the data input in these cases.
Round. When the rounding control is HIGH, the 24-bit sum of
products resulting from data input during that clock is rounded to 16
bits. When enabled rounding is automatically performed only during
the first cycle of each accumulation sequence, to avoid the
accumulation of roundoff errors.
Feedthrough. When the Feedthrough control is HIGH, the pipeline
delay through the cascade data path is minimized to simplify the
cascading of multiple devices. When FT is LOW and ADEL through
DDEL are all set to 0, the data inputs are aligned, such that
S(n+6) = CAS(n) + A(n)B(n) + C(n)D(n). See Table 2.
Cascade Enable. Data presented at the cascade data input port
are latched and accumulated internally when the input enable
CASEN during that clock is LOW. When CASEN is HIGH, the
cascade input port is ignored.
Accumulate. When the registered ACCumulator control is LOW, no
internal accumulation will be performed on the data input during the
current clock, effectively clearing the prior accumulated sum. When
ACC is HIGH, the internal accumulator adds the emerging product
to the sum of the previous products and RND is disabled.
Swap Output Words. The user may access both the most and
least-significant 16 bits of the 24-bit accumulator by utilizing SWAP.
Normal operation of the device, with SWAP = HIGH, outputs the
most significant word. Setting SWAP = LOW puts a double-register
structure into "toggle" mode, allowing the user to examine the LSW
on alternate clocks. New output data will not be clocked into the
output registers until SWAP returns HIGH.
Output Enable. Data currently in the output registers is available at
the output bus S
When OE is HIGH, the outputs are in the high-impedance state.
Do Not Connect
Index Pin (optional)
15-0
when the asynchronous Output Enable is LOW.
REV. 1.0.2 7/6/00
TMC2249A