MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 20

• Manufacturer Part Number: MPCBL5524A1D
• Manufacturer: Intel

Specifications of MPCBL5524A1D

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Introduction
2.3.11
2.3.12
2.3.13
2.3.14
20
Intel NetStructure
The ZT 5524 / MPCBL5524’s hot swap controller unconditionally resets the board when it detects
that the 3.3 V, 5 V, and 12 V supplies are below an acceptable operating limit. These limits are
defined as 4.75 V (5 V supply), 3.0 V (3.3 V supply), and 10.0 V (+12 V supply).
Fault current sensing is also provided. If a board fault (short circuit) or over-current condition is
detected, the hot swap controller automatically removes power from the ZT 5524 / MPCBL5524
components and the Status LED turns amber.
Reset
The ZT 5524 / MPCBL5524 provides the following reset types:
See
Two-Stage Watchdog Timer
The Watchdog Timer is an optional feature that monitors system operation and is programmable
for one of eight different timeout periods (from 0.25 s to 256 s). It is a two-stage watchdog,
meaning that it can be enabled to produce an NMI interrupt before it generates a system reset.
Failure to strobe the Watchdog Timer within the programmed time period may result in an NMI
interrupt, a system reset, or both.
A register bit is set if the watchdog timer caused the reset event. This Watchdog Timer is cleared on
power-up, enabling system software to take appropriate action on reboot. It is not cleared on reset
See
DMA
On-board peripherals can make use of the two enhanced 8237-style DMA controllers.
DMA channel 2 is assigned to the optional floppy drive.
The ZT 5524 / MPCBL5524’s DMA controllers reside in the ServerWorks CSB5 South Bridge
chipset. A link to the datasheet for this device is available in
Interrupts
Two enhanced 8259-style interrupt controllers provide the ZT 5524 / MPCBL5524 with a total of
15 interrupt inputs. Interrupt controller features include support for:
Interrupt sources include:
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Appendix C, “Reset,”
Chapter 6, “Watchdog
Push-button reset
Backplane reset input (J2 pin C17)
Watchdog timer reset
Level-triggered and edge-triggered inputs
Individual input masking
Fixed and rotating priorities
®
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
for more information.
Timer,”for more information.
Appendix E, “Chipset.”