MPCBL5524A1D Intel, MPCBL5524A1D Datasheet - Page 85

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MPCBL5524A1D

Manufacturer Part Number
MPCBL5524A1D
Description
Manufacturer
Intel
Datasheet

Specifications of MPCBL5524A1D

Lead Free Status / Rohs Status
Supplier Unconfirmed
C.1.3
Intel NetStructure
Note: For a diagram of the faceplate, see
NMI Sources
Abort Push Button (SW2)
When the Abort button (SW2) on the faceplate is pressed, it enables an NMI interrupt to the host
CPU controller.
The Watchdog Timer (Port 79h)
The watchdog timer can be programmed through the Watchdog Register (Port 79h, bit 4) to
generate a non-maskable interrupt if it is not strobed within a given time-out period. The Watchdog
Timer is discussed in
Rear-Panel Transition Board NMI Push Button
An NMI push button may be available on the optional RPIO transition board (such as the ZT 4807
Rear-Panel Transition Board). Pressing this button causes the ZT 5524 / MPCBL5524 to generate a
non-maskable interrupt.
®
CompactPCI bus push-button reset signal, PRST# (J2-C17)
PBRST- (J3-A4) generated by an RPIO transition board (e.g., the ZT 4807 Rear-Panel
Transition Board’s push button-switch SW2
ZT 5524 / MPCBL5524 High-Performance System Master Processor Board TPS
Chapter
6, the Watchdog Register specifications are on
Figure 1, “ZT 5524 / MPCBL5524 Faceplate” on page
page
73.
13.
Reset
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