LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 107

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFECP/EC6, LFECP/EC10, LFECP/EC15 Logic Signal Connections:
484 fpBGA (Cont.)
Number
AB10
AB11
AA12
AB12
AA13
AB13
AA14
AB14
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
AA18
AB20
AA19
GND
GND
GND
GND
GND
GND
W12
W13
W14
W15
W16
Ball
U11
U12
U13
U14
U15
U16
V12
Y12
T13
V13
Y13
V14
Y14
Y15
V15
T14
V16
Y17
V17
Y16
Function
PB16B
PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB21A
PB21B
PB22A
PB22B
PB23A
PB23B
PB24A
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
PB33B
GND5
GND4
GND4
GND4
Ball
NC
NC
NC
NC
NC
NC
NC
NC
NC
-
-
LFECP6/LFEC6
Bank LVDS
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PCLKC5_0
PCLKT5_0
VREF1_5
VREF1_4
VREF2_4
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
Function
WRITEN
BDQS22
BDQS30
CS1N
Dual
CSN
Number
AB10
AB11
AA12
AB12
AA13
AB13
AA14
AB14
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
AA18
AB20
AA19
GND
GND
GND
GND
GND
GND
W12
W13
W14
W15
W16
Ball
U11
U12
U13
U14
U15
U16
V12
Y12
T13
V13
Y13
V14
Y14
Y15
V15
T14
V16
Y17
V17
Y16
Function
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
PB41B
GND5
GND4
GND4
GND4
Ball
NC
NC
NC
NC
NC
NC
NC
NC
NC
-
-
LFECP10/LFEC10
Bank LVDS
4-41
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
-
-
-
-
-
-
-
-
-
-
-
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PCLKC5_0
PCLKT5_0
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
VREF1_5
VREF1_4
VREF2_4
Function
WRITEN
BDQS30
BDQS38
CS1N
Dual
CSN
LatticeECP/EC Family Data Sheet
Number
AB20
AA19
AB10
AB11
AA12
AB12
AA13
AB13
AA14
AB14
AB15
AB16
AA15
AB17
AA16
AB18
AA17
AB19
AA18
GND
GND
GND
GND
GND
GND
W12
W13
W14
W15
W16
Ball
V12
Y12
U11
U12
U13
V13
U14
Y13
V14
Y14
Y15
V15
U15
V16
U16
Y17
V17
Y16
T13
T14
Function
PB24B
PB25A
PB25B
PB26A
PB26B
PB27A
PB27B
PB28A
PB28B
PB29A
PB29B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B
PB33A
PB33B
PB34A
PB34B
PB35A
PB35B
PB36A
PB36B
PB37A
PB37B
PB38A
PB38B
PB39A
PB39B
PB40A
PB40B
PB41A
PB41B
PB42A
PB42B
PB43A
PB43B
PB44A
PB44B
PB45A
PB45B
PB46A
GND5
GND4
GND4
GND4
GND4
GND4
Ball
LFECP/LFEC15
Pinout Information
Bank LVDS
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
PCLKC5_0
PCLKT5_0
D0/SPID7
D2/SPID5
D1/SPID6
D3/SPID4
D4/SPID3
D5/SPID2
D6/SPID1
Function
VREF1_5
VREF1_4
VREF2_4
WRITEN
BDQS30
BDQS38
BDQS46
CS1N
Dual
CSN