LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 20

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-20. MAC sysDSP Element
MULTADD sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and A2. The user can enable the input, output and pipeline registers. Figure 2-21
shows the MULTADD sysDSP element.
Figure 2-21. MULTADD
Multiplicand
Multiplier
SignedAB
Addn
Accumsload
Shift Register B Out
Multiplicand A0
Multiplicand A1
Multiplier B0
Multiplier B1
Signed
Addn
Shift Register B In
Shift Register B Out
Shift Register B In
n
Register B
Input Data
n
n
Register B
Register B
Input Data
Input Data
n
n
n
n
n
n
Register
Register
Register
n
n
Input
Input
Input
Register
Register
m
Input
Input
Register A
Input Data
m
m
Register A
Register A
Input Data
Input Data
m
n
Shift Register A Out
Shift Register A In
m
Shift Register A Out
m
m
m
Register
Register
Pipeline
Pipeline
Register
Pipeline
Shift Register A In
m
m
Register
Pipeline
Register
Pipeline
m
n
Pipe
Pipe
Reg
Reg
m
n
m
n
Accumulator
Accumulator
Accumulator
2-17
Multiplier
To
To
To
Register
Pipeline
x
To Add/Sub
To Add/Sub
Multiplier
Multiplier
Register
Pipeline
Register
Pipeline
(default)
x
x
m+n
(default)
(default)
m+n
m+n
LatticeECP/EC Family Data Sheet
Accumulator
m+n+16 bits
Add/Sub
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
(default)
(default)
m+n+1
m+n+16 bits
(default)
(default)
m+n+1
Architecture
Output
Output
Overflow
signal