LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 12

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-8. Per Quadrant Primary Clock Selection
Figure 2-9. Per Quadrant Secondary Clock Selection
Figure 2-10. Slice Clock Selection
sysCLOCK Phase Locked Loops (PLLs)
The PLL clock input, from pin or routing, feeds into an input clock divider. There are three sources of feedback sig-
nal to the feedback divider: from CLKOP (PLL Internal), from clock net (CLKOP) or from a user clock (PIN or logic).
There is a PLL_LOCK signal to indicate that VCO has locked on to the input clock signal. Figure 2-11 shows the
sysCLOCK PLL diagram.
The setup and hold times of the device can be improved by programming a delay in the feedback or input path of
the PLL which will advance or delay the output clock with reference to the input clock. This delay can be either pro-
1. Smaller devices have fewer PLL related lines.
20 Secondary Clock Feedlines : 4 Clock Input Pads + 16 Routing Signals
4 Primary Clocks (CLK0, CLK1, CLK2, CLK3) per Quadrant
Secondary Clock
20 Primary Clock Sources: 12 PLLs + 4 PIOs + 4 Routing
Primary Clock
4 Secondary Clocks per Quadrant
Routing
GND
DCS
2-9
LatticeECP/EC Family Data Sheet
Clock to
each slice
DCS
1
Architecture