LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 2

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

May 2005
Features
■ Extensive Density and Package Options
■ sysDSP™ Block (LatticeECP™ Versions)
■ Embedded and Distributed Memory
■ Flexible I/O Buffer
Table 1-1. LatticeECP/EC Family Selection Guide
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or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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PFU/PFF Rows
PFU/PFF Columns
PFUs/PFFs
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
18x18 Multipliers
V
Number of PLLs
Packages and I/O Combinations:
100-pin TQFP (14 x 14 mm)
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
1. LatticeECP devices only.
CC
Voltage (V)
• 1.5K to 32.8K LUT4s
• 65 to 496 I/Os
• Density migration supported
• High performance multiply and accumulate
• 4 to 8 blocks
• 18 Kbits to 498 Kbits sysMEM™ Embedded
• Up to 131 Kbits distributed RAM
• Flexible memory resources:
• Programmable sysI/O™ buffer supports wide
Block RAM (EBR)
range of interfaces:
− 4 to 8 36x36 multipliers or
– 16 to 32 18x18 multipliers or
− 32 to 64 9x9 multipliers
− Distributed and block memory
Device
1
1
LFEC1
192
112
1.5
1.2
12
16
18
67
97
—
—
6
2
2
LatticeECP/EC Family Data Sheet
LFEC3
384
145
160
3.1
1.2
16
24
12
55
67
97
—
—
6
2
LFECP6
LFEC6/
1-1
768
147
195
224
6.1
1.2
24
32
25
92
10
16
97
■ Dedicated DDR Memory Support
■ sysCLOCK™ PLLs
■ System Level Support
■ Low Cost FPGA
4
2
• Implements interface up to DDR400 (200MHz)
• Up to four analog PLLs per device
• Clock multiply, divide and phase shifting
• IEEE Standard 1149.1 Boundary Scan, plus
• SPI boot flash interface
• 1.2V power supply
• Features optimized for mainstream applications
• Low cost TQFP and PQFP packaging
ispTRACY™ internal logic analyzer capability
LFECP10
LFEC10/
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− SSTL 3/2 Class I, II, SSTL18 Class I
− HSTL 18 Class I, II, III, HSTL15 Class I, III
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
1280
10.2
276
147
195
288
1.2
32
40
41
30
20
5
4
LFECP15
LFEC15/
1920
15.4
350
195
352
1.2
40
48
61
38
24
6
4
Introduction
LFECP20
LFEC20/
2464
19.7
424
360
400
1.2
44
56
79
46
28
7
4
Introduction_01.3
LFECP33
Data Sheet
LFEC33/
4096
32.8
131
498
360
496
1.2
64
64
54
32
8
4