LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 3

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Introduction
Lattice Semiconductor
LatticeECP/EC Family Data Sheet
Introduction
The LatticeECP/EC family of FPGA devices is optimized to deliver mainstream FPGA features at low cost. For
maximum performance and value, the LatticeECP™ (EConomy Plus) FPGA concept combines an efficient FPGA
fabric with high-speed dedicated functions. Lattice’s first family to implement this approach is the LatticeECP-
DSP™ (EConomy Plus DSP) family, providing dedicated high-performance DSP blocks on-chip. The LatticeEC™
(EConomy) family supports all the general purpose features of LatticeECP devices without dedicated function
blocks to achieve lower cost solutions.
The LatticeECP/EC FPGA fabric, which was designed from the outset with low cost in mind, contains all the critical
FPGA elements: LUT-based logic, distributed and embedded memory, PLLs and support for mainstream I/Os.
Dedicated DDR memory interface logic is also included to support this memory that is becoming increasingly prev-
alent in cost-sensitive applications.
®
The ispLEVER
design tool suite from Lattice allows large complex designs to be efficiently implemented using the
LatticeECP/EC FPGA family. Synthesis library support for LatticeECP/EC is available for popular logic synthesis
tools. The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to
place and route the design in the LatticeECP/EC device. The ispLEVER tool extracts the timing from the routing
and back-annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeECP/EC
family. By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their
design, increasing their productivity.
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