LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 24

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
For further information about the sysDSP block, please see the list of technical information at the end of this data
sheet.
Programmable I/O Cells (PIC)
Each PIC contains two PIOs connected to their respective sysI/O Buffers which are then connected to the PADs as
shown in Figure 2-24. The PIO Block supplies the output data (DO) and the Tri-state control signal (TO) to sysI/O
buffer, and receives input from the buffer.
Figure 2-24. PIC Diagram
Two adjacent PIOs can be joined to provide a differential I/O pair (labeled as “T” and “C”) as shown in Figure 2-25.
The PAD Labels “T” and “C” distinguish the two PIOs. Only the PIO pairs on the left and right edges of the device
can be configured as LVDS transmit/receive pairs.
One of every 16 PIOs contains a delay element to facilitate the generation of DQS signals. The DQS signal feeds
the DQS bus which spans the set of 16 PIOs. Figure 2-25 shows the assignment of DQS pins in each set of 16
PIOs. The exact DQS pins are shown in a dual function in the Logic Signal Connections table at the end of this data
sheet. Additional detail is provided in the Signal Descriptions table at the end of this data sheet. The DQS signal
from the bus is used to strobe the DDR data from the memory into input register blocks. This interface is designed
for memories that support one DQS strobe per eight bits of data.
DDRCLKPOL
ONEG1
ONEG0
OPOS1
OPOS0
IPOS0
IPOS1
GSRN
INDD
INCK
INFF
DQS
CLK
LSR
CE
TD
Control
Muxes
CLKO
CLKI
CEO
GSR
LSR
CEI
PIO B
PIO A
TD
D0
D1
DDRCLK
D0
D1
DDRCLK
INCK
INDD
INFF
IPOS0
IPOS1
Register Block
Register Block
Register Block
(2 Flip Flops)
(2 Flip Flops)
(5 Flip Flops)
2-21
Tristate
Output
Input
IOLD0
IOLT0
DI
LatticeECP/EC Family Data Sheet
Buffer
sysIO
PADB
PADA
"C"
"T"
Architecture