LFEC15E-5FN484C Lattice, LFEC15E-5FN484C Datasheet - Page 9

• Manufacturer Part Number: LFEC15E-5FN484C
• Description: FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Lattice

Specifications of LFEC15E-5FN484C

• Package: 484FBGA
• Family Name: LatticeEC
• Device Logic Units: 15400
• Maximum Internal Frequency: 420 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 352
• Ram Bits: 358400
• In System Programmability: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-5. Distributed Memory Primitives
ROM Mode: The ROM mode uses the same principal as the RAM modes, but without the Write port. Pre-loading is
accomplished through the programming interface during configuration.
PFU Modes of Operation
Slices can be combined within a PFU to form larger functions. Table 2-4 tabulates these modes and documents the
functionality possible at the PFU level.
Table 2-4. PFU Modes of Operation
1. These modes are not available in PFF blocks
MUX 16x1 x 1
MUX 2x1 x 8
MUX 4x1 x 4
MUX 8x1 x 2
LUT 6x 2 or
LUT 4x8 or
LUT 5x4 or
LUT 7x1 or
WRE
Logic
AD0
AD1
AD2
AD3
AD0
AD1
AD2
AD3
DI0
DI1
CK
ROM16x1
SPR16x2
2-bit Counter x 4
2-bit Comp x 4
2-bit Add x 4
2-bit Sub x 4
Ripple
DO0
DO0
DO1
2-6
DPR16x2 x 2
DPR16x4 x 1
SPR16x2 x 4
SPR16x4 x 2
SPR16x8 x 1
WAD0
WAD1
WAD2
WAD3
WCK
WRE
RAM
DI0
DI1
1
LatticeECP/EC Family Data Sheet
DPR16x2
ROM16x1 x 8
ROM16x2 x 4
ROM16x4 x 2
ROM16x8 x 1
ROM
RAD0
RAD1
RAD2
RAD3
RDO0
RDO1
WDO0
WDO1
Architecture