EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 213
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
© December 2010 Altera Corporation
Figure 8–24. JTAG Configuration of a Single Device Using a Download Cable (1.5-V or 1.8-V V
Powering the JTAG Pins)
Notes to
(1) Connect these pull-up resistors to the V
(2) Connect the nCONFIG and MSEL pins to support a non-JTAG configuration scheme. If you only use JTAG
(3) In the USB-Blaster and ByteBlaster II cables, this pin is connected to nCE when it is used for AS programming;
(4) The nCE must be connected to GND or driven low for successful JTAG configuration.
(5) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(6) Power up the V
(7) Resistor value can vary from 1 k to 10 k..
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
The Quartus II software verifies successful JTAG configuration after completion. At
the end of configuration, the software checks the state of CONF_DONE through the
JTAG port. When Quartus II generates a .jam for a multi-device chain, it contains
instructions so that all the devices in the chain are initialized at the same time. If
CONF_DONE is not high, the Quartus II software indicates that configuration has
failed. If CONF_DONE is high, the software indicates that configuration was successful.
After the configuration bitstream is serially sent using the JTAG TDI port, the TCK
port clocks an additional clock cycles to perform device initialization.
configuration, connect the nCONFIG pin to logic-high and the MSEL pins to GND. In addition, pull DCLK and
DATA[0] to either high or low, whichever is convenient on your board.
otherwise it is a no connect.
Ethernet-Blaster, ByteBlaster II, and USB-Blaster cables do not support a target supply voltage of 1.2 V. For the target
supply voltage value, refer to the
Guide, and the
Figure
10 kΩ
V
CCIO
8–24:
(1)
EthernetBlaster Communications Cable User
V
CC
CCIO
of the EthernetBlaster, ByteBlaster II or USB-Blaster cable with supply from V
10 kΩ
GND
(1)
(2)
(2)
(2)
(2)
N.C. (5)
ByteBlaster II Download Cable User
nCE (4)
nCEO
nSTATUS
CONF_DONE
nCONFIG
DATA[0]
DCLK
MSEL[ ]
Cyclone IV Device
CCIO
supply of the bank in which the pin resides.
TDO
TMS
TCK
TDI
(7)
Guide.
V
CCIO
V
CCIO
Guide, the
(7)
1 kΩ
GND
Cyclone IV Device Handbook, Volume 1
Download Cable 10-Pin Male
Pin 1
USB-Blaster Download Cable User
Header (Top View)
GND
V
CCIO (6)
CCIO
V
IO
(3)
. The
GND
CCIO
8–47
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