EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 83
![IC CYCLONE IV FPGA 15K 169FBGA](/photos/6/73/67316/169-fbga_sml.jpg)
EP4CGX15BF14C8N
Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX15BF14C8N
Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CGX15BF14C8N
Manufacturer:
ALTERA33
Quantity:
276
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
External Clock Outputs
© December 2010 Altera Corporation
f
Each PLL of Cyclone IV devices supports one single-ended clock output or one
differential clock output. Only the C0 output counter can feed the dedicated external
clock outputs, as shown in
output counters can feed other I/O pins through the GCLK.
Figure 5–11
Figure 5–11. External Clock Outputs for PLLs
Notes to
(1) These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
(2) PLL#_CLKOUTp and PLL#_CLKOUTn pins are dual
Each pin of a differential output pair is 180° out of phase. The Quartus II software
places the NOT gate in your design into the I/O element to implement 180° phase
with respect to the other pin in the pair. The clock output pin pairs support the same
I/O standards as standard output pins.
To determine which I/O standards are supported by the PLL clock input and output
pins, refer to the
Cyclone IV PLLs can drive out to any regular I/O pin through the GCLK. You can also
use the external clock output pins as GPIO pins if external PLL clocking is not
required.
output or one differential clock output. When using both pins as single
output while the other pin is configured as a regular user I/O.
Figure
shows the external clock outputs for PLLs.
5–11:
Cyclone IV Device I/O Features
Figure
PLL#
5–11, without going through the GCLK. Other
clkena 0 (1)
C0
C1
C2
C3
C4
PLL#_CLKOUTp (2)
-
purpose I/O pins that you can use as one single
chapter.
PLL#_CLKOUTn (2)
-
ended I/Os, one of them can be the clock
Cyclone IV Device Handbook, Volume 1
clkena 1 (1)
-
ended clock
5–21
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