EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 49

IC CYCLONE IV FPGA 15K 169FBGA

EP4CGX15BF14C8N

Manufacturer Part Number
EP4CGX15BF14C8N
Description
IC CYCLONE IV FPGA 15K 169FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr

Specifications of EP4CGX15BF14C8N

Number Of Logic Elements/cells
14400
Number Of Labs/clbs
900
Total Ram Bits
540000
Number Of I /o
72
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
169-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1475

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Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
Figure 3–12. Cyclone IV Devices Shift Register Mode Configuration
ROM Mode
FIFO Buffer Mode
© November 2009 Altera Corporation
f
w × m × n Shift Register
W
W
W
W
Figure 3–12
Cyclone IV devices M9K memory blocks support ROM mode. A .mif initializes the
ROM contents of these blocks. The address lines of the ROM are registered. The
outputs can be registered or unregistered. The ROM read operation is identical to the
read operation in the single-port RAM configuration.
Cyclone IV devices M9K memory blocks support single-clock or dual-clock FIFO
buffers. Dual clock FIFO buffers are useful when transferring data from one clock
domain to another clock domain. Cyclone IV devices M9K memory blocks do not
support simultaneous read and write from an empty FIFO buffer.
For more information about FIFO buffers, refer to the
Megafunction User
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
m-Bit Shift Register
shows the Cyclone IV devices M9K memory block in shift register mode.
Guide.
W
W
W
W
Single- and Dual-Clock FIFO
Cyclone IV Device Handbook, Volume 1
n Number of Taps
3–13

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