EP4CGX15BF14C8N Altera, EP4CGX15BF14C8N Datasheet - Page 381

• Manufacturer Part Number: EP4CGX15BF14C8N
• Description: IC CYCLONE IV FPGA 15K 169FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX15BF14C8N

• Number Of Logic Elements/cells: 14400
• Number Of Labs/clbs: 900
• Total Ram Bits: 540000
• Number Of I /o: 72
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 169-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-1475

Chapter 2: Cyclone IV Reset Control and Power Down
Transceiver Reset Sequences
© December 2010 Altera Corporation
As shown in
manual lock mode:
1. After power up, assert pll_areset for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the multipurpose PLL locks, as indicated by the pll_locked signal going
4. Wait for at least t
5. Deassert rx_digitalreset at least t
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal deasserted
during this time period. After you deassert the pll_areset signal, the
multipurpose PLL starts locking to the transmitter input reference clock.
high (marker 3), deassert tx_digitalreset. For receiver operation, after
deassertion of busy signal, wait for two parallel clock cycles to deassert the
rx_analogreset signal.
rx_locktorefclk signal. At the same time, assert the rx_locktodata signal
(marker 7). At this point, the receiver CDR enters lock-to-data mode and the
receiver CDR starts locking to the received data.
after asserting the rx_locktodata signal. At this point, the transmitter and
receiver are ready for data traffic.
Figure
2–9, perform the following reset procedure for the receiver in
LTR_LTD_Manual
(the time between markers 6 and 7), then deassert the
LTD_Manual
(the time between markers 7 and 8)
Cyclone IV Device Handbook, Volume 2
2–15