EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 220

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N

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Duty Cycle Distortion
5–84
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
DDIO Column Output I/O
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2)
DDIO Column Output I/O
Table 5–84
The DCD specification is based on a no logic array noise condition.
Standard
Table
Standard
5–84:
assumes the input clock has zero DCD.
Notes
Notes
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
3.3/2.5 V
150
255
175
170
155
140
150
150
150
125
240
180
(1),
(1),
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
TTL/CMOS
3.3/2.5 V
(2)
(2)
440
390
375
325
430
355
350
Clock Port (No PLL in the Clock Path)
1.8/1.5 V
TTL/CMOS
265
370
295
290
275
260
270
270
270
240
360
180
Clock Port (No PLL in the Clock Path)
1.8/1.5 V
495
450
430
385
490
410
405
SSTL-2
2.5 V
140
155
180
85
65
60
55
70
60
60
55
85
SSTL/HSTL
SSTL-2
1.8/1.5 V
2.5 V
170
120
105
160
90
85
80
140
155
180
85
65
60
50
70
60
60
55
85
SSTL/HSTL
1.8/1.5 V
1.2-V
HSTL
1.2 V
140
155
180
85
65
60
50
70
60
60
55
85
160
110
100
155
Altera Corporation
95
75
70
April 2011
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