EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 80

no-image

EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
450
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
531
Part Number:
EP2S90F1020I4N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
0
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
100
Price:
1.00 USD
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
1 072
Price:
1.00 USD
Part Number:
EP2S90F1020I4NK
Manufacturer:
ALTERA
0
I/O Structure
Figure 2–47. Row I/O Block Connection to the Interconnect
Note to
(1)
2–72
Stratix II Device Handbook, Volume 1
Interconnect
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
LAB Local
Figure
Interconnects
to Adjacent LAB
R4 & R24
Interconnect
2–47:
Direct Link
LAB
io_dataina[3..0]
io_datainb[3..0]
C4 Interconnect
to Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Note (1)
Interconnect
io_clk[7:0]
32
Horizontal
I/O Block
up to Four IOEs
Block Contains
Horizontal I/O
Altera Corporation
32 Data & Control
Signals from
Logic Array (1)
May 2007

Related parts for EP2S90F1020I4N