EP2S90F1020I4N Altera, EP2S90F1020I4N Datasheet - Page 5

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EP2S90F1020I4N

Manufacturer Part Number
EP2S90F1020I4N
Description
IC STRATIX II FPGA 90K 1020-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet

Specifications of EP2S90F1020I4N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520488
Number Of I /o
758
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1020-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
90960
# I/os (max)
758
Frequency (max)
711.24MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520488
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1920
EP2S90F1020I4N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
450
Price:
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
EP2S90F1020I4N
Manufacturer:
ALTERA
Quantity:
531
Price:
Altera Corporation
May 2007
Notes to
(1)
(2)
(3)
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
Pitch (mm)
Area (mm2)
Length × width
(mm × mm)
Table 1–2. Stratix II Package Options & I/O Pin Counts
Table 1–3. Stratix II FineLine BGA Package Sizes
Dimension
Device
All I/O pin counts include eight dedicated clock input pins (clk1p, clk1n, clk3p, clk3n, clk9p, clk9n,
clk11p, and clk11n) that can be used for data inputs.
The Quartus II software I/O pin counts include one additional pin,
purpose I/O pins. The PLL_ENA pin can only be used to enable the PLLs within the device.
The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages
include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and
FPLL10CLKp/n) that can be used for data inputs.
(3)
(3)
Table
(3)
(3)
1–2:
FineLine BGA
484-Pin
484 Pin
23 × 23
342
342
334
1.00
529
Stratix II devices are available in space-saving FineLine BGA
(see
All Stratix II devices support vertical migration within the same package
(for example, you can migrate between the EP2S15, EP2S30, and EP2S60
devices in the 672-pin FineLine BGA package). Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
To ensure that a board layout supports migratable densities within one
package offering, enable the applicable vertical migration path within the
Quartus II software (Assignments menu > Device > Migration Devices).
FineLine
Tables 1–2
484-Pin
Hybrid
484-Pin
27 × 27
Hybrid
BGA
308
1.00
729
and 1–3).
FineLine
672-Pin
672 Pin
27 × 27
BGA
366
500
492
1.00
729
Notes
FineLine
780-Pin
BGA
534
534
PLL_ENA
780 Pin
29 × 29
(1),
1.00
841
Stratix II Device Handbook, Volume 1
(2)
FineLine BGA
, which is not available as general-
1,020-Pin
1,020 Pin
718
758
742
742
33 × 33
1,089
1.00
FineLine BGA
1,508-Pin
®
Introduction
1,508 Pin
packages
40 × 40
1,126
1,170
1,600
902
1.00
1–3

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