CY7C64713-128AXC Cypress Semiconductor Corp, CY7C64713-128AXC Datasheet - Page 17

• Manufacturer Part Number: CY7C64713-128AXC
• Description: IC MCU USB EZ FX1 16KB 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-128AXC

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1678; CY7C64713-128AXC

CY7C64713 Pin Definitions
The FX1 Pin Definitions for CY7C64713 follow.
Table 8. FX1 Pin Definitions
Note
Document #: 38-08039 Rev. *F
TQFP
6. Do not leave unused inputs floating. Tie either HIGH or LOW as appropriate. Pull outputs up or down to ensure signals at power up and in standby. Note that no pins
128
120
126
127
128
117
118
119
17
13
20
19
18
94
95
96
97
21
22
23
24
25
59
60
61
62
63
86
87
88
39
34
10
must be driven when the device is powered down.
TQFP
100
16
12
19
18
17
28
9
SSOP
56
10
14
13
17
16
15
QFN
56
10
3
7
6
9
8
AVCC
AVCC
AGND
AGND
DMINUS
DPLUS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
PSEN#
BKPT
Name
Type
Power
Power
Ground
Ground
I/O/Z
I/O/Z
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Output
Output
[6]
Default
N/A
N/A
N/A
N/A
H
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Analog VCC. Connect this pin to 3.3V power source. This signal
provides power to the analog section of the chip.
Analog VCC. Connect this pin to 3.3V power source. This signal
provides power to the analog section of the chip.
Analog Ground. Connect to ground with as short a path as possible.
Analog Ground. Connect to ground with as short a path as possible.
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
8051 Address Bus. This bus is driven at all times. When the 8051 is
addressing the internal RAM it reflects the internal address.
8051 Data Bus. This bidirectional bus is high impedance when
inactive, input for bus reads, and output for bus writes. The data bus is
used for external 8051 program and data memory. The data bus is
active only for external bus accesses, and is driven LOW in suspend.
Program Store Enable. This active LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x4000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
Breakpoint. This pin goes active (HIGH) when the 8051 address bus
matches the BPADDRH/L registers and breakpoints are enabled in the
BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT
register is HIGH, this signal pulses HIGH for eight 12-/24-/48 MHz
clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the
8051 clears the BREAK bit (by writing ‘1’ to it) in the BREAKPT register.
Description
CY7C64713
Page 17 of 55
[+] Feedback