CY7C64713-128AXC Cypress Semiconductor Corp, CY7C64713-128AXC Datasheet - Page 43

• Manufacturer Part Number: CY7C64713-128AXC
• Description: IC MCU USB EZ FX1 16KB 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-128AXC

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1678; CY7C64713-128AXC

The following table provides the Slave FIFO Synchronous Address Parameters.
Table 27. Slave FIFO Synchronous Address Parameters
Slave FIFO Asynchronous Address
In the following figure, dashed lines indicate signals with programmable polarity.
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz
Table 28. Slave FIFO Asynchronous Address Parameters
Document #: 38-08039 Rev. *F
t
t
t
t
t
Slave FIFO Synchronous Address
IFCLK
SFA
FAH
SFA
FAH
Parameter
Parameter
Interface Clock Period
FIFOADR[1:0] to Clock Setup Time
Clock to FIFOADR[1:0] Hold Time
FIFOADR[1:0] to RD/WR/PKTEND Setup Time
RD/WR/PKTEND to FIFOADR[1:0] Hold Time
SLCS/FIFOADR [1:0]
SLCS/FIFOADR [1:0]
RD/WR/PKTEND
Figure 29. Slave FIFO Asynchronous Address Timing Diagram
Figure 28. Slave FIFO Synchronous Address Timing Diagram
IFCLK
Description
Description
t
SFA
t
SFA
t
FAH
[16]
20.83
t
Min
Min
FAH
25
10
10
10
Max
200
Unit
ns
ns
.
CY7C64713
Unit
ns
ns
ns
Page 43 of 55
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