CY7C64713-128AXC Cypress Semiconductor Corp, CY7C64713-128AXC Datasheet - Page 32

• Manufacturer Part Number: CY7C64713-128AXC
• Description: IC MCU USB EZ FX1 16KB 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-128AXC

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1678; CY7C64713-128AXC

AC Electrical Characteristics
USB Transceiver
USB 2.0 compliant in full speed mode.
Table 11. Program Memory Read Parameters
Document #: 38-08039 Rev. *F
Notes
t
t
t
t
t
t
t
t
CL
AV
STBL
STBH
SOEL
SCSL
DSU
DH
12. CLKOUT is shown with positive polarity.
13. t
CLKOUT
Parameter
t
t
ACC1
ACC1
ACC1
A[15..0]
(24 MHz) = 3*t
(48 MHz) = 3*t
PSEN#
is computed from the parameters in
D[7..0]
CS#
OE#
[12]
1/CLKOUT Frequency
Delay from Clock to Valid Address
Clock to PSEN Low
Clock to PSEN High
Clock to OE Low
Clock to CS Low
Data Setup to Clock
Data Hold Time
CL
CL
– t
– t
t
AV
AV
AV
t
CL
– t
– t
DSU
DSU
t
SOEL
t
SCSL
= 106 ns
= 43 ns.
Description
Table 11
Figure 12. Program Memory Read Timing Diagram
t
STBL
t
as follows:
ACC1
[13]
data in
Min
9.6
0
0
0
0
t
STBH
t
DH
20.83
41.66
83.2
Typ
t
AV
Max
10.7
11.1
13
8
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CY7C64713
48 MHz
24 MHz
12 MHz
Notes
Page 32 of 55
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