CY7C64713-128AXC Cypress Semiconductor Corp, CY7C64713-128AXC Datasheet - Page 22

• Manufacturer Part Number: CY7C64713-128AXC
• Description: IC MCU USB EZ FX1 16KB 128LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-128AXC

• Program Memory Type: ROMless
• Package / Case: 128-LQFP
• Applications: USB Microcontroller
• Core Processor: 8051
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 40
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Processor Series: CY7C64xx
• Core: M8C
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C/USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3674
• Minimum Operating Temperature: 0 C
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: TQFP
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 40
• Ram Memory Size: 16KB
• Cpu Speed: 48MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Compliant
• Other names: 428-1678; CY7C64713-128AXC

Table 8. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *F
TQFP
128
106
69
70
71
66
67
98
32
28
31
30
29
53
52
51
50
42
41
40
38
TQFP
100
54
55
56
51
52
76
26
22
84
25
24
23
43
42
41
40
32
31
SSOP
56
36
37
38
20
QFN
56
29
30
31
13
CTL0 or
FLAGA
CTL1 or
FLAGB
CTL2 or
FLAGC
CTL3
CTL4
CTL5
IFCLK
INT4
INT5#
T2
T1
T0
RXD1
TXD1
RXD0
TXD0
CS#
WR#
RD#
OE#
Name
Type
O/Z
O/Z
O/Z
O/Z
Output
Output
I/O/Z
Input
Input
Input
Input
Input
Input
Output
Input
Output
Output
Output
Output
Output
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
H
H
H
H
H
H
H
H
Z
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0]
pins.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
Interface Clock, used for synchronously clocking data into or out of the
slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is used
(IFCONFIG.7 = 1) the IFCLK pin is configured to output 30/48 MHz by
bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether
internally or externally sourced, by setting the bit IFCONFIG.4 = 1.
INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is
edge-sensitive, active HIGH.
INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is
edge-sensitive, active LOW.
T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides
the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not
use this pin.
T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the
input to Timer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use
this bit.
T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the
input to Timer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use
this bit.
RXD1is an active-HIGH input signal for 8051 UART1, which provides
data to the UART in all modes.
TXD1is an active-HIGH output pin from 8051 UART1, which provides
the output clock in sync mode, and the output data in async mode.
RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides
data to the UART in all modes.
TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in async
mode.
CS# is the active-LOW chip select for external memory.
WR# is the active-LOW write strobe output for external memory.
RD# is the active-LOW read strobe output for external memory.
OE# is the active LOW output enable for external memory.
Description
CY7C64713
Page 22 of 55
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