PNX1501E/G,557 NXP Semiconductors, PNX1501E/G,557 Datasheet - Page 104
![IC MEDIA PROC 266MHZ 456-BGA](/photos/6/76/67605/568-456-bga_sot795-1_sml.jpg)
PNX1501E/G,557
Manufacturer Part Number
PNX1501E/G,557
Description
IC MEDIA PROC 266MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1502EG557.pdf
(828 pages)
Specifications of PNX1501E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Other names
568-1297
935277747557
PNX1501E/G
935277747557
PNX1501E/G
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Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
10.3.1 PCI Capabilities
10.2 IR Remote Control Receiver and Blaster
10.3 PCI-2.2 & XIO-16 Bus Interface Unit
This allows use of GPIO for a variety of functions.
PNX15xx Series uses the GPIO pin event sequence timestamping mechanism and
software to interpret remote control commands. The event sequence timestamping
can resolve events on signal edges with 75 ns accuracy. A sequence of events
followed by a period of inactivity causes generation of an interrupt. Software then
interprets the ‘character’ by looking at the event list consisting of (time, direction)
encoded in memory.
This allows interpretation of a wide variety of Remote Control protocols. The Philips
RC-5, RC-6 and RC-MM remote control protocols are all decoded with this
mechanism, provided that the RF demodulation is performed externally. Most other
Consumer Electronic vendor remote control protocols can be supported by
appropriate software.
Similarly, the event generation mechanism can be used to implement IR blaster
capability. In this case, the modulator is included - the software generated pulses can
be superimposed on an internally generated carrier.
There are some speed considerations with this mechanism. Each character
communicated generates at least one interrupt, and possibly more if the number of
edge events exceeds the FIFO size. Hence, this mechanism is suitable only for
protocols that use frequencies up to a few 10’s of kHz, with low character repetition
rates, and not for high speed protocols.
PNX15xx Series contains an expansion bus interface unit ‘PCI/XIO-16’ that allows
easy connection of a variety of board level memory components and peripherals. The
bus interface is a single set of pins that allows simultaneous connection of 32-bit PCI
master/slave devices as well as separated address/data style 8- and 16-bit micro
processor slave peripherals and standard (NOR) or disk-type (NAND) Flash memory.
The bus interface unit contains a built-in single-channel DMA unit that can move
blocks of data to or from an external peripheral (PCI bus master or slave) to or from
PNX15xx Series DRAM. The DMA unit can access PCI as well as 8- and 16-bit wide
XIO devices. The DMA unit packs XIO device data to/from 32-bit words, so that no
CPU involvement is required to pre/post process data.
PNX15xx Series complies with Revision 2.2 of the PCI bus specification, and
operates as a 32-bit PCI master/target up to 33 MHz.
PNX15xx Series as PCI master allows TM3260 to generate all single cycle PCI
transaction types, including memory cycles, I/O cycles, configuration cycles and
interrupt acknowledge cycles. As PCI target, PNX15xx Series responds to memory
transactions and configuration type cycles, but not to I/O cycles.
•
•
50% of the pins will have a ‘low’ reset value
50% have a ‘high’ reset value
Rev. 3 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 2: Overview
2-23
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