PNX1501E/G,557 NXP Semiconductors, PNX1501E/G,557 Datasheet - Page 578
![IC MEDIA PROC 266MHZ 456-BGA](/photos/6/76/67605/568-456-bga_sot795-1_sml.jpg)
PNX1501E/G,557
Manufacturer Part Number
PNX1501E/G,557
Description
IC MEDIA PROC 266MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1502EG557.pdf
(828 pages)
Specifications of PNX1501E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Other names
568-1297
935277747557
PNX1501E/G
935277747557
PNX1501E/G
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Philips Semiconductors
Volume 1 of 1
Table 6: SPDIF Input Registers
PNX15XX_SER_3
Product data sheet
Bit
5
4
3
2
1
0
Offset 0x10 AFE8
31:10
9
8
7
6
5
4
3
2
1
0
Offset 0x10 AFEC
31:10
9
Symbol
PERR_ENBL
OVR_ENBL
HBE_ENBL
BUF1_ACTIVE_ENBL
BUF2_FULL_ENBL
BUF1_FULL_ENBL
Unused
UNLOCK_CLR
UCBITS_CLR
LOCK_CLR
VERR_CLR
PERR_CLR
OVR_CLR
HBE_CLR
BUF1_ACTIVE_CLR
BUF2_FULL_CLR
BUF1_FULL_CLR
Unused
UNLOCK_SET
SPDI_INTCLR
SPDI_INTSET
…Continued
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
W
W
W
W
W
W
W
Value
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
-
0
Rev. 3 — 17 March 2006
Description
1 = PERR bit in SPDI_STATUS is enabled for interrupts.
0 = PERR bit in SPDI_STATUS is disabled for interrupts.
1 = OVERRUN bit in SPDI_STATUS is enabled for interrupts.
0 = OVERRUN bit in SPDI_STATUS is disabled for interrupts.
1 = HBE bit in SPDI_STATUS is enabled for interrupts.
0 = HBE bit in SPDI_STATUS is disabled for interrupts.
1 = BUF1_ACTIVE bit in SPDI_STATUS is enabled for interrupts.
0 = BUF1_ACTIVE bit in SPDI_STATUS is disabled for interrupts.
1 = BUF2_FULL bit in SPDI_STATUS is enabled for interrupts.
0 = BUF2_FULL bit in SPDI_STATUS is disabled for interrupts.
1 = BUF1_FULL bit in SPDI_STATUS is enabled for interrupts.
0 = BUF1_FULL bit in SPDI_STATUS is disabled for interrupts.
1 = Clear UNLOCK bit in SPDI_STATUS.
0 = No effect
1 = Clear UCBITS in SPDI_STATUS.
0 = No effect.
1 = Clears LOCK in SPDI_STATUS.
0 = No effect.
1 = Clear VERR in SPDI_STATUS.
0 = No effect
1 = Clear PERR in SPDI_STATUS.
0 = No effect.
1 = Clear OVERRUN in SPDI_STATUS.
0 = No effect.
1 = Clear HBE in SPDI_STATUS.
0 = No effect.
1 = Clear BUF1_ACTIVE in SPDI_STATUS.
0 = No effect.
1 = Clear BUF2_FULL in SPDI_STATUS.
0 = No effect.
SPDI_BASE1 must be valid before setting BUF2_FULL_CLR.
1 = Clear BUF1_FULL in SPDI_STATUS.
0 = No effect.
SPDI_BASE1 must be valid before setting BUF1_FULL_CLR.
1 = UNLOCK bit in SPDI_STATUS is to be set to logic ‘1’. Level
trigger interrupt will be raised to the external interrupt controller if
the corresponding enable bit is set to logic ‘1’.
0 = No effect
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 18: SPDIF Input
18-22
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