PNX1501E/G,557 NXP Semiconductors, PNX1501E/G,557 Datasheet - Page 142
![IC MEDIA PROC 266MHZ 456-BGA](/photos/6/76/67605/568-456-bga_sot795-1_sml.jpg)
PNX1501E/G,557
Manufacturer Part Number
PNX1501E/G,557
Description
IC MEDIA PROC 266MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1502EG557.pdf
(828 pages)
Specifications of PNX1501E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Other names
568-1297
935277747557
PNX1501E/G
935277747557
PNX1501E/G
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1. Introduction
2. Functional Description
The Reset module initiates life for the PNX15xx Series system since it generates all
reset signals required for a correct initialization of the entire system (may include
board devices).
These resets signals are triggered by hardware (one type) or by software (three
types):
RST_CAUSE MMIO register holds the cause of the previous reset which allows the
software to know what happened before.
The Reset module generates three different reset signals to fully initialize a PNX15xx
Series system:
Remark: The JTAG state machine can also be reset through the JTAG pins.
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Chapter 4: Reset
PNX15xx Series Data Book – Volume 1 of 1
Rev. 3 — 17 March 2006
It sends reset signals to all DCS bus modules and the TM3260 CPU.
It sends a reset signal on the SYS_RST_OUT_N pin that can be used by external
board devices. This signal is then de-asserted by software.
Hardware external reset input to the PNX15xx Series through the pins,
POR_IN_N or RESET_IN_N.
Software assert and release of the SYS_RST_OUT_N reset pin through a write
to an MMIO register write.
Software programmable watchdog timer which asserts the same reset signals as
the hardware reset induced by the assertion of RESET_IN_N pin when a time-out
is reached.
Software PNX15xx Series system reset which asserts the same reset signals as
the hardware reset induced by the assertion of RESET_IN_N pin.
jtag_rst_n. This signal is used internally to reset the JTAG state machine. The
signal is only asserted if the POR_IN_N pin is asserted. Therefore the only mean
to reset the JTAG state machine of PNX15xx Series is by asserting the
POR_IN_N
pin.Figure 1
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