Z9035112PSC Zilog, Z9035112PSC Datasheet - Page 101

• Manufacturer Part Number: Z9035112PSC
• Description: IC 64KW DIG TV CTRL OTP 52-SDIP
• Manufacturer: Zilog

Specifications of Z9035112PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (128 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 2K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 25
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 52-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1.
2.
The Op Code (0000001) provides a unique signature for the LD command. The
processor uses this signature to determine the instruction format. The RAM bank bit is
high (equal to 1) because of the instruction definition b=1 (Pn:b). The destination bit
code is 0011 which corresponds to the accumulator. The source 0110 corresponds to the
+1 option and P2:0 or P2:1. The RAM bank bit indicates that the processor loaded the
accumulator with the operand designated by Pointer 2 Bank1 (P2:1).
Source and destination fields can be accessed from the register pointers, data pointers, or
registers. The Op Code specifies the type of source and destination. An Op Code of
0000101 specifies that the source is an indirect address to program memory (@@P0.0
or @D0:0) and the destination is a register.
Instruction formats and applicable instructions are listed in Table 66 through Table 72.
The Variables a, op, b, d, s, cc, am, fm, rp are used in the
instruction format to depict bits determined by the instruction.
The General Instruction Format requires an Op Code, RAM bank bit, destination
and source addresses. For example, LD A, @P2:1+