Z9035112PSC Zilog, Z9035112PSC Datasheet - Page 26

• Manufacturer Part Number: Z9035112PSC
• Description: IC 64KW DIG TV CTRL OTP 52-SDIP
• Manufacturer: Zilog

Specifications of Z9035112PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (128 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 2K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 25
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 52-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The 1K words RAM is organized in four banks of 256 words consisting of 16 bits each.
Bankl.0 is always accessible. Bank0.0 is mapped to other bank(s); only one gauge from 0.X
is active through bit selection. See Figure 7.
The processor is able to operate from several clock sources:
•
•
•
In addition, the processor clock can be halted temporarily to select the clock source or
access ROM without disrupting normal operation of the processor.
An external crystal controls the internal 32.768-kHz oscillator. The crystal is used as the
clock reference for the internal Phase Locked Loop (PLL). The PLL provides the internal
PVCO clock for processor operation. SCLK is generated internally by dividing the
frequency of an appropriate oscillator (PVCO) by 2. The frequency of the SCLK after
POR is 12.058 MHz.
The SCLK signal can be sent to the Port16 output pin under software control by setting bit
9 in register R3(1). The SVCO must be used as the system clock when the OSD is
generated.
The clock switch control register R6(1) defines the source of the SCLK for the Z90356
core. The block diagram in Figure 8 represents the clock switch circuit.
Bank1.0
words
256
Primary Phase Lock Loop VCO source (PVCO)
Secondary Phase Lock Loop (SVCO)
32.768-kHz oscillator clock (OSC)
Bank0.0
words
256
Bank0.1
256
Bank0.2
256