Z9035112PSC Zilog, Z9035112PSC Datasheet - Page 49

• Manufacturer Part Number: Z9035112PSC
• Description: IC 64KW DIG TV CTRL OTP 52-SDIP
• Manufacturer: Zilog

Specifications of Z9035112PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (128 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 2K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 25
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 52-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization occurs by setting the Cursor_Info_Load bit R7(3)<4> to 1, then writing
sequentially to the R3(3) 16-bit parameters (COLOR, HPARAM, VPARAM and CADDR,
respectively).
The cursor buffer is loaded from ROM at the leading edge of HSYNC wherever the
horizontal line requires a cursor. This process halts the CPU for 3/5/7 cycles depending on
the cursor’s horizontal size. The cursor bitmap address pointer (CADDR) is incremented
automatically.
Though the cursor can be displayed anywhere on the screen, limiting the cursor to the
OSD area is best. Outside of the OSD area, the cursor can jitter or become distorted.
The cursor bitmap is organized as pixel data placed sequentially in the ROM. The data
format is described below.
For the interlaced mode, even and odd cursor bitmaps must be defined separately. Proper
selection occurs during the cursor initialization at the beginning of every field. See Figure
23, Table 13, and Table 14.
LD
OR
LD
LD
LD
LD
AND
SR,%#60; select RegBank3
EXT7,#%0010; enable Cursor_Info_Load
EXT3,#(3*64 + 7*8 + 2); load CCOLOR: color3 = 3, color2 = 7, color1 = 2
EXT3,#(2*1024 + 120); load HPARAM: hsize = 2 (32 pixels), hpos = 120
EXT3,#(28*1024 + 55); load VPARAM: vsize = 28, vpos = 55
EXT3,#%6000; load CADDR—cursor bitmap address
EXT7,#%FFEF; disable Cursor_Info_Load, ready for OSD