Z9035112PSC Zilog, Z9035112PSC Datasheet - Page 73

• Manufacturer Part Number: Z9035112PSC
• Description: IC 64KW DIG TV CTRL OTP 52-SDIP
• Manufacturer: Zilog

Specifications of Z9035112PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (128 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 2K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 25
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 52-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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The SVCO/PVCO bit when read back determines the current setting of the system clock.
Writing a 1 to this bit switches the system clock from its current setting to PVCO. This
switch has a glitch filter that removes random voltage spikes. It must be changed back to
PVCO. The Z90356 switches to the SVCO automatically when it receives an H-sync
interrupt. This mechanism exists to synchronize the system clock exactly with the H-sync
trailing edge. The result is a sharp start of the OSD, jitter free.
An example of a typical SVCO/PVCO switching follows:
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Use the following procedure when changing from Switching VCO to permanent
PVCO while running from the fast clock:
Use the following procedure when changing from permanent PVCO to Switching
VCO while running from the fast clock.
System clock is set to PVCO.
H-sync interrupt occurs. (The system clock has automatically been set to the
SVCO). OSD code is executed inside of the H-sync Interrupt Service Routine (ISR).
Before leaving the ISR, the user switches the clock back to PVCO.
Simultaneously set the H_position delay to 0x0, while leaving the No_switch
enabled (0), and the SVCO/PVCO left as (0).
Wait a minimum of 80 clock cycles to flush any H-sync out of the system.
Simultaneously Switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>),
while leaving the No_switch enabled (0), and the H_position delay at 0x0.
Wait for 3 system clock cycles to be sure that the clock has had time to switch
to PVCO.
Switch No_switch to No clock switch (write 1 into R6(1)<6>). The
H_position can be set to none-zero at this time as well.
Simultaneously set the H_position delay to 0x0, while leaving the No_switch
disabled (1), and the SVCO/PVCO setting as don’t care (0).
Wait a minimum of 80 clock cycles to flush residual H-sync out of the system.
Simultaneously switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>), while
leaving the No_switch disabled (1), and the H_position delay at 0x0.
Wait 3 system clock cycles to be sure that the clock has had time to switch to
PVCO.
Switch No_switch to Clock switching is Enabled (write 0 into R6(1)<6>). The
H_position can be set to none-zero at this time as well.