Z9035112PSC Zilog, Z9035112PSC Datasheet - Page 37

• Manufacturer Part Number: Z9035112PSC
• Description: IC 64KW DIG TV CTRL OTP 52-SDIP
• Manufacturer: Zilog

Specifications of Z9035112PSC

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (128 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 2K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 25
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 52-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

The first module, the Master, can be configured for fast (400 kHz) or slow (100 kHz) bit
rates and can be used in applications with a single master.
The second module, the Slave, supports a 7-bit addressing format with both fast and slow
bit rates.
The Z90356 adds two additional nonstandard bit rates (50 kHz and 10 kHz) and an additional
multiplexed master port that is controlled by the I
Table 8 lists the bit rates for the Master I
To suppress possible problems on both data (SDA) and clock (SCL) lines, digital filters
are available for all inputs of the I
equal to 3T
If the Master or Slave I
the slave, Port11 and Port12 for the master) must be assigned as outputs.
Master and Slave modules cannot be used simultaneously because of the shared I
register (see the register R3(0) data field). The software activates I
appropriate commands into the control register. To control the I
control register R3(0) toggle bit <c> must point to an appropriate interface (Master or
Slave).
M_disable or S_disable bits allow either the Master or Slave I
so as not to interfere with any activity associated with the Port pins. At Power-on Reset
(POR), both I
pin (multiplexed with the I
M_disable or S_disable bits must be reset to 0.
External register R3(0) controls the I
commands. Table 10 lists the Slave I
are flow charts of the Master and Slave modes.
Â
SCLK
2
C interfaces are enabled. To use the I
= 250 ns.
!
!
2
C interface is enabled, corresponding I/Os (Port01 and Port02 for
2
C Data and Clock) must be configured as an output, while
2
C bus interface. These filters exhibit a time constant
2
2
C bus interface commands. Figure 16 and Figure 17
C. Table 9 lists the Master I
2
C Bus.
2
CM_mux control bit.
2
C interface, the corresponding Port
2
2
C interface to be disabled
C bus interface, the
2
2
C bus interface
C modules by writing
2
C data