Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 24
Z84C2008PEG
Manufacturer Part Number
Z84C2008PEG
Description
IC 8MHZ Z80 CMOS PIO 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C2008PEG
Processor Type
Z80
Features
Low Power CMOS
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z84C2xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C2008PEG
Manufacturer:
Zilog
Quantity:
20
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4
UM008005-0205
Z80 CPU
User’s Manual
unlimited subroutine nesting and simplification of many types of data
manipulation.
Two Index Registers (IX and IY)
The two independent index registers hold a 16-bit base address that is used
in indexed addressing modes. In this mode, an index register is used as a
base to point to a region in memory from which data is to be stored or
retrieved. An additional byte is included in indexed instructions to specify a
displacement from this base. This displacement is specified as a two's
complement signed integer. This mode of addressing greatly simplifies
many types of programs, especially where tables of data are used.
Interrupt Page Address Register (I)
The Z80 CPU can be operated in a mode where an indirect call to any
memory location can be achieved in response to an interrupt. The
is used for this purpose and stores the high order eight bits of the indirect
address while the interrupting device provides the lower eight bits of the
address. This feature allows interrupt routines to be dynamically located
anywhere in memory with minimal access time to the routine.
Memory Refresh Register (R)
The Z80 CPU contains a memory refresh counter, enabling dynamic
memories to be used with the same ease as static memories. Seven bits of
this 8-bit register are automatically incremented after each instruction fetch.
The eighth bit remains as programmed, resulting from an LD R, A
instruction. The data in the refresh counter is sent out on the lower portion of
the address bus along with a refresh control signal while the CPU is
decoding and executing the fetched instruction. This mode of refresh is
transparent to the programmer and does not slow the CPU operation. The
programmer can load the
normally not used by the programmer. During refresh, the contents of the
register are placed on the upper eight bits of the address bus.
R
register for testing purposes, but this register is
I
Overview
register
I
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