Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 32
![IC 8MHZ Z80 CMOS PIO 40-DIP](/photos/6/57/65796/269-40-dip_sml.jpg)
Z84C2008PEG
Manufacturer Part Number
Z84C2008PEG
Description
IC 8MHZ Z80 CMOS PIO 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C2008PEG
Processor Type
Z80
Features
Low Power CMOS
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z84C2xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C2008PEG
Manufacturer:
Zilog
Quantity:
20
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12
UM008005-0205
Z80 CPU
User’s Manual
CLK
Instruction Fetch
T Cycle
T1
Figure 4.
Figure 5 depicts the timing during an M1 (opcode fetch) cycle. The PC is
placed on the address bus at the beginning of the M1 cycle. One half clock
cycle later the MREQ signal goes active. At this time the address to the
memory has had time to stabilize so that the falling edge of MREQ can be
used directly as a chip enable clock to dynamic memories. The RD line also
goes active to indicate that the memory read data should be enabled onto the
CPU data bus. The CPU samples the data from the memory on the data bus
with the rising edge of the clock of state T3 and this same edge is used by
the CPU to turn off the RD and MREQ signals. Thus, the data has already
been sampled by the CPU before the RD signal becomes inactive. Clock
state T3 and T4 of a fetch cycle are used to refresh dynamic memories. The
CPU uses this time to decode and execute the fetched instruction so that no
other operation could be performed at this time.
During T3 and T4, the lower seven bits of the address bus contain a memory
refresh address and the RFSH signal becomes active tindicating that a
refresh read of all dynamic memories must be accomplished. An RD signal
is not generated during refresh time to prevent data from different memory
Machine Cycle
(Opcode Fetch)
T2
M1
Basic CPU Timing Example
T3
Instruction Cycle
T1
(Memory Read)
M2
T2
T3
T1
(Memory Write)
M3
T2
T3
Overview
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