Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 44

• Manufacturer Part Number: Z84C2008PEG
• Description: IC 8MHZ Z80 CMOS PIO 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C2008PEG

• Processor Type: Z80
• Features: Low Power CMOS
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z84C2xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24
UM008005-0205
Z80 CPU
User’s Manual
CPU Response
Action
DI Instruction Execution
EI Instruction Execution
LD A,I Instruction Execution *
LD A,R instruction Execution *
Accept NMI
RETN Instruction Execution IFF2 *
Table 2. Interrupt Enable/Disable, Flip-Flops
Non-Maskable
The CPU always accepts a non-maskable interrupt. When this occurs, the
CPU ignores the next instruction that it fetches and instead performs a
restart to location 0066H. The CPU functions as if it had recycled a restart
instruction, but to a location other than one of the eight software restart
locations. A restart is merely a call to a specific address in page 0 of
memory.
The CPU can be programmed to respond to the maskable interrupt in any
one of three possible modes.
Mode 0
This mode is similar to the 8080A interrupt response mode. With this mode,
the interrupting device can place any instruction on the data bus and the
CPU executes it. Thus, the interrupting device provides the next instruction
to be executed. Often this is a restart instruction because the interrupting
device only need supply a single byte instruction. Alternatively, any other
IFF1 IFF2 Comments
0
0
1
0
1
*
*
*
Maskable INT Disabled
IFF2 → indicates completion of non-
Maskable, INT Enabled
IFF2 → Parity Flag
IFF2 → Parity Flag
Maskable Interrupt
maskable interrupt service routine.
Overview