Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 91

• Manufacturer Part Number: Z84C2008PEG
• Description: IC 8MHZ Z80 CMOS PIO 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C2008PEG

• Processor Type: Z80
• Features: Low Power CMOS
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z84C2xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UM008005-0205
is transferred in the upper half of the address bus. In all register indirect
input output instructions, including block I/O transfers, the content of
register C is transferred to the lower half of the address bus (device
address) while the content of register B is transferred to the upper half of
the address bus.
CPU Control Group
Table 20 illustrates the six general-purpose CPU control instructions. The
NOP
operation until a subsequent interrupt is received, while the
used to lock out and enable interrupts. The three interrupt mode
commands set the CPU to any of the three available interrupt response
modes as follows. If Mode 0 is set, the interrupting device can insert any
instruction on the data bus and allow the CPU to execute it. Mode 1 is a
simplified mode where the CPU automatically executes a restart (
location
content is pushed onto the stack). Mode 2 is the most powerful because it
allows for an indirect call to any location in memory. With this mode, the
CPU forms a 16-bit memory address where the upper eight bits are the
content of register I and the lower eight bits are supplied by the
interrupting device. This address points to the first of two sequential bytes
in a table where the address of the service routine is located. The CPU
automatically obtains the starting address and performs a
instruction to this address.
Address of Interrupt
Service Routine
is a do-nothing instruction. The
0038H
so that no external hardware is required (the old PC
Pointer to Interrupt Table,
Register I is Upper Address,
Peripheral Supplies
Lower Address
HALT
Z80 CPU Instruction Description
instruction suspends CPU
User’s Manual
CALL
DI
Z80 CPU
and
RST
E1
) to
are
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