Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 42

• Manufacturer Part Number: Z84C2008PEG
• Description: IC 8MHZ Z80 CMOS PIO 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C2008PEG

• Processor Type: Z80
• Features: Low Power CMOS
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z84C2xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

22
INTERRUPT RESPONSE
UM008005-0205
Z80 CPU
User’s Manual
Overview
Interrupt Enable/Disable
An interrupt allows peripheral devices to suspend CPU operation and force
the CPU to start a peripheral service routine. This service routine usually
involves the exchange of data, status, or control information between the
CPU and the peripheral. When the service routine is completed, the CPU
returns to the operation from which it was interrupted.
The Z80 CPU has two interrupt inputs, a software maskable interrupt (INT)
and a non-maskable interrupt (NMI). The non-maskable interrupt cannot be
disabled by the programmer and is accepted whenever a peripheral device
requests it. This interrupt is generally reserved for very important functions
that can be enabled or disabled selectively by the programmer. This routine
allows the programmer to disable the interrupt during periods when his
program has timing constraints that do not allow interrupt. In the Z80 CPU,
there is an interrupt enable flip-flop (IFF) that is set or reset by the
programmer using the Enable Interrupt (EI) and Disable Interrupt (DI)
instructions. When the IFF is reset, an interrupt cannot be accepted by the
CPU.
The two enable flip-flops are IFF1 and IFF2.
The state of IFF1 is used to inhibit interrupts while IFF2 is used as a
temporary storage location for IFF1.
Disables interrupts
from being accepted
IFF1
location for IFF1
Temporary storage
IFF2
Overview