Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 38
Z84C2008PEG
Manufacturer Part Number
Z84C2008PEG
Description
IC 8MHZ Z80 CMOS PIO 40-DIP
Manufacturer
Zilog
Series
Z80r
Specifications of Z84C2008PEG
Processor Type
Z80
Features
Low Power CMOS
Speed
8MHz
Voltage
5V
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Cpu Speed
8MHz
Digital Ic Case Style
DIP
No. Of Pins
40
Supply Voltage Range
5V
Operating Temperature Range
-40°C To +100°C
Svhc
No SVHC (18-Jun-2010)
Rohs Compliant
Yes
Processor Series
Z84C2xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Base Number
84
Clock Frequency
8MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z84C2008PEG
Manufacturer:
Zilog
Quantity:
20
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18
UM008005-0205
Z80 CPU
User’s Manual
HALT Exit
A
15
MREQ
RFSH
— A
CLK
NMI
RD
Figure 10. Non-Maskable Interrupt Request Operation
Whenever a software HALT instruction is executed, the CPU executes
NOPs until an interrupt is received (either a non-maskable or a maskable
interrupt while the interrupt flip-flop is enabled). The two interrupt lines are
sampled with the rising clock edge during each T4 state as depicted in
Figure 11. If a non-maskable interrupt has been received or a maskable
interrupt has been received and the interrupt enable flip-flop is set, then the
HALT state is exited on the next rising clock edge. The following cycle is an
interrupt acknowledge cycle corresponding to the type of interrupt that was
received. If both are received at this time, then the non-maskable one is
acknowledged since it has highest priority. The purpose of executing NOP
instructions while in the HALT state is to keep the memory refresh signals
active. Each cycle in the HALT state is a normal M1 (fetch) cycle except
that the data received from the memory is ignored and a NOP instruction is
forced internally to the CPU. The HALT acknowledge signal is active
during this time indicating that the processor is in the HALT state.
M1
0
Last M Cycle
Last T State
T
1
PC
T
2
M1
T
3
Refresh
T
4
Overview
T
1
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