Z84C2008PEG Zilog, Z84C2008PEG Datasheet - Page 28

• Manufacturer Part Number: Z84C2008PEG
• Description: IC 8MHZ Z80 CMOS PIO 40-DIP
• Manufacturer: Zilog
• Series: Z80r

Specifications of Z84C2008PEG

• Processor Type: Z80
• Features: Low Power CMOS
• Speed: 8MHz
• Voltage: 5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Cpu Speed: 8MHz
• Digital Ic Case Style: DIP
• No. Of Pins: 40
• Supply Voltage Range: 5V
• Operating Temperature Range: -40°C To +100°C
• Svhc: No SVHC (18-Jun-2010)
• Rohs Compliant: Yes
• Processor Series: Z84C2xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 16
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• Base Number: 84
• Clock Frequency: 8MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8
UM008005-0205
Z80 CPU
User’s Manual
BUSACK
Bus Acknowledge (output, active Low). Bus Acknowledge indicates to the
requesting device that the CPU address bus, data bus, and control signals
MREQ, IORQ RD, and WR have entered their high-impedance states. The
external circuitry can now control these lines.
BUSREQ
Bus Request (input, active Low). Bus Request has a higher priority than
NMI and is always recognized at the end of the current machine cycle.
BUSREQ forces the CPU address bus, data bus, and control signals MREQ
IORQ, RD, and WR to go to a high-impedance state so that other devices
can control these lines. BUSREQ is normally wired-OR and requires an
external pull-up for these applications. Extended BUSREQ periods due to
extensive DMA operations can prevent the CPU from properly refreshing
dynamic RAMS.
D7–D0
Data Bus (input/output, active High, tristate). D7–D0 constitute an
8-bit bidirectional data bus, used for data exchanges with memory and I/O.
HALT
HALT State (output, active Low). HALT indicates that the CPU has
executed a HALT instruction and is waiting for either a non-maskable or a
maskable interrupt (with the mask enabled) before operation can resume.
During HALT, the CPU executes NOPs to maintain memory refresh.
INT
Interrupt Request (input, active Low). Interrupt Request is generated by
I/O devices. The CPU honors a request at the end of the current instruction if
the internal software-controlled interrupt enable flip-flop (IFF) is enabled.
INT is normally wired-OR and requires an external
pull-up for these applications.
Overview