CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 12

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

External Interface
Processor RESET and Initialization
Processor initialization or start up is accomplished with
activation (HIGH) of the RESET pin. The 80C86 RESET is
required to be HIGH for greater than 4 CLK cycles. The 80C86
will terminate operations on the high-going edge of RESET and
will remain dormant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset sequence for
approximately 7 CLK cycles. After this interval, the 80C86
operates normally beginning with the instruction in absolute
ADDR/DATA
RD, INTA
STATUS
READY
ADDR/
S2-S0
DT/R
DEN
CLK
ALE
WR
t1
A15-A0
12
A19-A16
BHE,
MEMORY ACCESS TIME
t2
(4 + NWAIT) = TCY
WAIT
BUS RESERVED
FOR DATA IN
t3
READY
FIGURE 3. BASIC SYSTEM TIMING
S7-S3
tWAIT
D15-D0
VALID
80C86
t4
location FFFF0H (see Figure 2). The RESET input is internally
synchronized to the processor clock. At initialization, the
HIGH-to-LOW transition of RESET must occur no sooner than
50µs (or 4 CLK cycles, whichever is greater) after power-up, to
allow complete initialization of the 80C86.
NMl will not be recognized prior to the second CLK cycle
following the end of RESET. If NMl is asserted sooner than nine
clock cycles after the end of RESET, the processor may
execute one instruction before responding to the interrupt.
t1
A19-A16
A15-A0
BHE
t2
GOES INACTIVE IN THE STATE
(4 + NWAIT) = TCY
WAIT
JUST PRIOR TO t4
DATA OUT (D15-D0)
t3
READY
tWAIT
S7-S3
t4
January 9, 2009
FN2957.3