CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 13

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate need for pull-up/down resistors,
“bus-hold” circuitry has been used on the 80C86 pins 2-16,
26-32 and 34-39 (see Figures 4A and 4B). These circuits will
maintain the last valid logic state if no driving source is present
(i.e., an unconnected pin or a driving source which goes to a
high impedance state). To overdrive the “bus hold” circuits, an
external driver must be capable of supplying approximately
400µA minimum sink or source current at valid input voltage
levels. Since this “bus hold” circuitry is active and not a
“resistive” type element, the associated power supply current is
negligible and power dissipation is significantly reduced when
compared to the use of passive pull-up resistors.
Interrupt Operations
Interrupt operations fall into two classes: software or
hardware initiated. The software initiated interrupts and
software aspects of hardware interrupts are specified in the
“Instruction Set Summary” on page 31. Hardware interrupts
can be classified as non-maskable or maskable.
Interrupts result in a transfer of control to a new program
location. A 256-element table containing address pointers to
the interrupt service program locations resides in absolute
locations 0 through 3FFH, which are reserved for this
purpose. Each element in the table is 4 bytes in size and
corresponds to an interrupt “type”. An interrupting device
supplies an 8-bit type number during the interrupt
acknowledge sequence, which is used to “vector” through the
appropriate element to the new interrupt service program
location. All flags and both the Code Segment and Instruction
Pointer register are saved as part of the lNTA sequence.
OUTPUT
OUTPUT
DRIVER
DRIVER
BUFFER
BUFFER
INPUT
INPUT
FIGURE 4A. BUS HOLD CIRCUITRY PINS 2-16, 34-39
FIGURE 4B. BUS HOLD CIRCUITRY PINS 26-32
V
FIGURE 4. INTERNAL BUS HOLD DEVICES
CC
P
PROTECTION
PROTECTION
CIRCUITRY
CIRCUITRY
INPUT
INPUT
13
BOND
BOND
PAD
PAD
EXTERNAL
PIN
EXTERNAL
PIN
80C86
These are restored upon execution of an Interrupt Return
(IRET) instruction.
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a
LOW-to-HIGH transition. The activation of this pin causes a
type 2 interrupt.
NMl is required to have a duration in the HIGH state of
greater than two CLK cycles, but is not required to be
synchronized to the clock. Any positive transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves of a block-type
instruction. Worst case response to NMI would be for
multiply, divide, and variable shift instructions. There is no
specification on the occurrence of the low-going edge; it may
occur before, during or after the servicing of NMI. Another
positive edge triggers another response if it occurs after the
start of the NMI procedure. The signal must be free of logical
spikes in general and be free of bounces on the low-going
edge to avoid triggering extraneous responses.
Maskable Interrupt (INTR)
The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the
resetting of the interrupt enable flag (IF) status bit. The
interrupt request signal is level triggered. It is internally
synchronized during each clock cycle on the high-going
edge of CLK. To be responded to, lNTR must be present
(HIGH) during the clock period preceding the end of the
current instruction or the end of a whole move for a block
type instruction. lNTR may be removed anytime after the
falling edge of the first INTA signal. During the interrupt
response sequence further interrupts are disabled. The
enable bit is reset as part of the response to any interrupt
(lNTR, NMI, software interrupt or single-step), although the
FLAGS register which is automatically pushed onto the stack
reflects the state of the processor prior to the interrupt. Until
the old FLAGS register is restored, the enable bit will be zero
unless specifically set by an instruction.
During the response sequence (see Figure 5) the processor
executes two successive (back-to-back) interrupt acknowledge
cycles. The 80C86 emits the LOCK signal (Max mode only)
from t2 of the first bus cycle until t2 of the second. A local bus
“hold” request will not be honored until the end of the second
bus cycle. In the second bus cycle, a byte is supplied to the
80C86 by the 82C59A Interrupt Controller, which identifies the
source (type) of the interrupt. This byte is multiplied by 4 and
used as a pointer into the interrupt vector lookup table. An INTR
signal left HIGH will be continually responded to within the
limitations of the enable bit and sample period. The
INTERRUPT RETURN instruction includes a FLAGS pop
which returns the status of the original interrupt enable bit
when it restores the FLAGS.
January 9, 2009
FN2957.3