CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 6

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V
mode are described; all other pin functions are as described in the following.
Maximum Mode System
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique
to maximum mode are described in the following.
SYMBOL
SYMBOL
HOLD
HLDA
S0
S1
S2
NUMBER
NUMBER
31, 30
PIN
PIN
26
27
28
6
TYPE
TYPE
O
O
O
O
I
(Continued)
HOLD: indicates that another master is requesting a local bus “hold”. To be an acknowledged, HOLD
must be active HIGH. The processor receiving the “hold” will issue a “hold acknowledge” (HLDA) in
the middle of a t4 or TI clock cycle. Simultaneously with the issuance of HLDA, the processor will float
the local bus and control lines. After HOLD is detected as being LOW, the processor will lower HLDA,
and when the processor needs to run another cycle, it will again drive the local bus and control lines.
HOLD is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the setup time.
STATUS: is active during t4, t1 and t2 and is returned to the passive state (1, 1, 1) during t3 or during
tW when READY is HIGH. This status is used by the 82C88 Bus Controller to generate all memory
and I/O access control signals. Any change by S2, S1 or S0 during t4 is used to indicate the beginning
of a bus cycle, and the return to the passive state in t3 or tW is used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one state during “grant sequence”.
S2
0
0
0
0
1
1
1
1
80C86
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
DESCRIPTION
DESCRIPTION
CC
Interrupt Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
). Only the pin functions which are unique to minimum
CHARACTERISTICS
January 9, 2009
FN2957.3