CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 14

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

.
Halt
When a software “HALT” instruction is executed, the
processor indicates that it is entering the “HALT” state in one
of two ways depending upon which mode is strapped. In
minimum mode, the processor issues one ALE with no
qualifying bus control signals. In maximum mode the
processor issues appropriate HALT status on S2, S1, S0 and
the 82C88 bus controller issues one ALE. The 80C86 will not
leave the “HALT” state when a local bus “hold” is entered
while in “HALT”. In this case, the processor reissues the
HALT indicator at the end of the local bus hold. An NMI or
interrupt request (when interrupts enabled) or RESET will
force the 80C86 out of the “HALT” state.
Read/Modify/Write (Semaphore)
Operations Via Lock
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the execution
of an instruction. This gives the processor the capability of
performing read/modify/write operations on memory (via the
Exchange Register With Memory instruction, for example)
without another system bus master receiving intervening
memory cycles. This is useful in multiprocessor system
configurations to accomplish “test and set lock” operations. The
LOCK signal is activated (forced LOW) in the clock cycle
following decoding of the software “LOCK” prefix instruction. It
is deactivated at the end of the last bus cycle of the instruction
following the “LOCK” prefix instruction. While LOCK is active a
request on a RQ/GT pin will be recorded and then honored at
the end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C86 provides a single
software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
repeatedly executed until the TEST input goes active (LOW).
The execution of WAIT does not consume bus cycles once
the queue is full.
If a local bus request occurs during WAIT execution, the
80C86 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold
LOCK
AD15
AD0-
INTA
ALE
FIGURE 5. INTERRUPT ACKNOWLEDGE SEQUENCE
t1
FLOAT
t2
t3
t4 TI
14
t1
t2
VECTOR
TYPE
t3
t4
80C86
circuits. If interrupts are enabled, the 80C86 will recognize
interrupts and process them when it regains control of the
bus. The WAIT instruction is then refetched, and
re-executed.
Basic System Timing
Typical system configurations for the processor operating in
minimum mode and in maximum mode are shown in
Figures 6A and 6B, respectively. In minimum mode, the
MN/MX pin is strapped to VCC and the processor emits bus
control signals (e.g. RD, WR, etc.) directly. In maximum
mode, the MN/MX pin is strapped to GND and the processor
emits coded status information which the 82C88 bus
controller uses to generate MULTIBUS compatible bus
control signals. Figure 3 shows the signal timing
relationships.
System Timing - Minimum System
The read cycle begins in t1 with the assertion of the Address
Latch Enable (ALE) signal. The trailing (low-going) edge of
this signal is used to latch the address information, which is
valid on the address/data bus (AD0-AD15) at this time, into
the 82C82/82C83 latch. The BHE and A0 signals address
the low, high or both bytes. From t1 to t4 the M/lO signal
indicates a memory or I/O operation. At t2, the address is
removed from the address/data bus and the bus is held at
the last valid logic state by internal bus hold devices. The
read control signal is also asserted at t2. The read (RD)
signal causes the addressed device to enable its data bus
drivers to the local bus. Some time later, valid data will be
available on the bus and the addressed device will drive the
READY line HIGH. When the processor returns the read
signal to a HIGH level, the addressed device will again
three-state its bus drivers. If a transceiver (82C86/82C87) is
AX
BX
CX
DX
FLAGS
TABLE 4. 80C86 REGISTER
AH
BH
CH
DH
H
BP
CS
DS
SP
SS
ES
DI
SI
IP
FLAGS
AL
BL
CL
DL
L
ACCUMULATOR
BASE
COUNT
DATA
STACK POINTER
BASE POINTER
SOURCE INDEX
DESTINATION INDEX
INSTRUCTION POINTER
STATUS FLAG
CODE SEGMENT
DATA SEGMENT
STACK SEGMENT
EXTRA SEGMENT
January 9, 2009
FN2957.3