CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 15

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

required to buffer the 80C86 local bus, signals DT/R and
DEN are provided by the 80C86.
A write cycle also begins with the assertion of ALE and the
emission of the address. The M/IO signal is again asserted
to indicate a memory or I/O write operation. In t2,
immediately following the address emission, the processor
emits the data to be written into the addressed location. This
data remains valid until at least the middle of t4. During t2, t3
and tW, the processor asserts the write control signal. The
write (WR) signal becomes active at the beginning of t2 as
opposed to the read which is delayed somewhat into t2 to
provide time for output drivers to become inactive.
The BHE and A0 signals are used to select the proper
byte(s) of the memory/lO word to be read or written
according to Table 5.
I/O ports are addressed in the same manner as memory
location. Even addressed bytes are transferred on the
D7-D0 bus lines and odd address bytes on D15-D8.
The basic difference between the interrupt acknowledge
cycle and a read cycle is that the interrupt acknowledge
signal (INTA) is asserted in place of the read (RD) signal and
the address bus is held at the last valid logic state by internal
bus hold devices (see Figure 4). In the second of two
successive INTA cycles a byte of information is read from
the data bus (D7-D0) as supplied by the interrupt system
BHE
0
0
1
1
A0
0
1
0
1
Whole word
Upper Byte From/To Odd Address
Lower Byte From/To Even Address
None
TABLE 5.
15
CHARACTERISTICS
80C86
logic (i.e., 82C59A Priority Interrupt Controller). This byte
identifies the source (type) of the interrupt. It is multiplied by
4 and used as a pointer into an interrupt vector lookup table,
as described earlier.
Bus Timing - Medium Size Systems
For medium complexity systems the MN/MX pin is
connected to GND and the 82C88 Bus Controller is added to
the system as well as an 82C82/82C83 latch for latching the
system address, and an 82C86/82C87 transceiver to allow
for bus loading greater than the 80C86 is capable of
handling. Signals ALE, DEN, and DT/R are generated by the
82C88 instead of the processor in this configuration,
although their timing remains relatively the same. The
80C86 status outputs (S2, S1 and S0) provide type-of-cycle
information and become 82C88 inputs. This bus cycle
information specifies read (code, data or I/O), write (data or
I/O), interrupt acknowledge, or software halt. The 82C88
issues control signals specifying memory read or write, I/O
read or write, or interrupt acknowledge. The 82C88 provides
two types of write strobes, normal and advanced, to be
applied as required. The normal write strobes have data
valid at the leading edge of write. The advanced write
strobes have the same timing as read strobes, and hence,
data is not valid at the leading edge of write. The
82C86/82C87 transceiver receives the usual T and OE
inputs from the 82C88 DT/R and DEN signals.
The pointer into the interrupt vector table, which is passed
during the second INTA cycle, can be derived from an
82C59A located on either the local bus or the system bus. If
the master 82C59A Priority Interrupt Controller is positioned
on the local bus, the 82C86/82C87 transceiver must be
disabled when reading from the master 82C59A during the
interrupt acknowledge sequence and software “poll”.
January 9, 2009
FN2957.3