CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 26

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Waveforms
NOTES:
19. Signals at 82C84A or 82C86 are shown for reference only.
20. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
21. Status inactive in state just prior to t4.
22. Cascade address is valid between first and second INTA cycles.
23. Two INTA cycles run back-to-back. The 80C86 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown
82C88 CEN.
for second INTA cycle.
SEE NOTES
SEE NOTES 18, 19
OUTPUTS
82C88 OUTPUTS
SOFTWARE
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH
82C88
18, 19
S2, S1, S0 (EXCEPT HALT)
(Continued)
(SEE NOTES 21, 22)
AMWC OR AIOWC
MWTC OR IOWC
WRITE CYCLE
INTA CYCLE
TCHSV (21)
26
MCE/PDEN
AD15-AD0
AD15-AD0
AD15-AD0
AD
(28) TSVMCH
15
(30) TCLMCH
DT/R
-AD
INTA
CLK
DEN
DEN
(25) TCLAZ
S2
FIGURE 8B. BUS TIMING - MAXIMUM MODE (USING 82C88)
0
TCHSV
TCLAV
(21)
(23)
TCLAV
(18) TCLML
(18) TCLML
(23)
TCLMCL
CASCADE ADDR
TCVNV
RESERVED FOR
(35)
t1
TCLAX
TCLDV
TCHDTL
(41)
80C86
INVALID ADDRESS
TCVNV
(35)
TCLSH
(32)
(22)
(33)
(24)
(18)TCLML
t2
TCLSH
(19) TCLMH
(6)
(22)
TCLMH
DATA
TCVNX
t3
(19)
TDVCL
(36)
POINTER
tW
(SEE NOTE 20))
TCVNX (36)
TCLDX2
t4
TCLMH (19)
TCLDX1 (7)
(42)
TCHDTH
(34)
January 9, 2009
FN2957.3