CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 9

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Word (16-bit) operands can be located on even or odd
address boundaries and are thus, not constrained to even
boundaries as is the case in many 16-bit computers. For
address and data operands, the least significant byte of the
word is stored in the lower valued address location and the
most significant byte in the next higher address location. The
BIU automatically performs the proper number of memory
accesses; one, if the word operand is on an even byte
boundary and two, if it is on an odd byte boundary. Except
for the performance penalty, this double access is
transparent to the software. The performance penalty does
not occur for instruction fetches; only word operands.
Physically, the memory is organized as a high bank
(D15-D8) and a low bank (D7-D0) of 512k bytes addressed
in parallel by the processor’s address lines.
Byte data with even addresses is transferred on the D7-D0
bus lines, while odd addressed byte data (A0 HIGH) is
transferred on the D15-D8 bus lines. The processor provides
two enable signals, BHE and A
from or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the
processor at the byte level as necessary.
In referencing word data, the BlU requires one or two memory
cycles depending on whether the starting byte of the word is
on an even or odd address, respectively. Consequently, in
referencing word operands performance can be optimized by
locating data on even address boundaries. This is an
especially useful technique for using the stack, since odd
address references to the stack may adversely affect the
context switching time for interrupt processing or task
multiplexing.
Certain locations in memory are reserved for specific CPU
operations (see Figure 2). Locations from address FFFF0H
through FFFFFH are reserved for operations including a jump
to the initial program loading routine. Following RESET, the
CPU will always begin execution at location FFFF0H where
the jump must be located. Locations 00000H through 003FFH
are reserved for interrupt operations. Each of the 256 possible
interrupt service routines is accessed through its own pair of
16-bit pointers (segment address pointer and offset address
pointer). The first pointer, used as the offset address, is
loaded into the lP and the second pointer, which designates
the base address is loaded into the CS. At this point, program
control is transferred to the interrupt routine. The pointer
elements are assumed to have been stored at the respective
places in reserved memory prior to occurrence of interrupts.
Minimum and Maximum Operation Modes
The requirements for supporting minimum and maximum
80C86 systems are sufficiently different that they cannot be
met efficiently using 40 uniquely defined pins. Consequently,
the 80C86 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain
9
0
, to selectively allow reading
80C86
subset of the pins changes, dependent on the condition of the
strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum mode.
When the MN/MX pin is strapped to V
generates bus control signals itself on pins 24 through 31
and 34.
The minimum mode 80C86 can be used with either a
multiplexed or demultiplexed bus. This architecture provides
the 80C86 processing power in a highly integrated form.
The demultiplexed mode requires two 82C82 latches (for 64k
addressability) or three 82C82 latches (for a full megabyte of
addressing). An 82C86 or 82C87 transceiver can also be
used if data bus buffering is required (see Figure 6A.) The
80C86 provides DEN and DT/R to control the transceiver, and
ALE to latch the addresses. This configuration of the minimum
mode provides the standard demultiplexed bus structure with
heavy bus buffering and relaxed bus timing requirements.
The maximum mode employs the 82C88 bus controller (see
Figure 6B). The 82C88 decodes status lines S0, S1 and S2,
and provides the system with all bus control signals.
Moving the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
lock, queue status, and two request/grant interfaces are
provided by the 80C86 in maximum mode. These features
allow coprocessors in local bus and remote bus
configurations.
Bus Operation
The 80C86 has a combined address and data bus
commonly referred to as a time multiplexed bus. This
technique provides the most efficient use of pins on the
processor while permitting the use of a standard 40 lead
package. This “local bus” can be buffered directly and used
throughout the system with address latching provided on
memory and I/O modules. In addition, the bus can also be
demultiplexed at the processor with a single set of 82C82
address latches if a standard non-multiplexed bus is desired
for the system.
Each processor bus cycle consists of at least 4 CLK cycles.
These are referred to as t1, t2, t3 and t4 (see Figure 3). The
address is emitted from the processor during t1 and data
transfer occurs on the bus during t3 and t4. t2 is used
primarily for changing the direction of the bus during read
operations. In the event that a “NOT READY” indication is
given by the addressed device, “Wait” states (tW) are
inserted between t3 and t4. Each inserted wait state is the
same duration as a CLK cycle. Periods can occur between
80C86 driven bus cycles. These are referred to as idle”
states (T
cycles for internal housekeeping and processing.
During t1 of any bus cycle, the ALE (Address Latch Enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
I
) or inactive CLK cycles. The processor uses these
CC
, the 80C86
January 9, 2009
FN2957.3