CP80C86-2Z Intersil, CP80C86-2Z Datasheet - Page 5

• Manufacturer Part Number: CP80C86-2Z
• Description: IC CPU 16BIT 5V 8MHZ 40-PDIP
• Manufacturer: Intersil

Specifications of CP80C86-2Z

• Processor Type: 80C86 16-Bit
• Speed: 8MHz
• Voltage: 4.5 ~ 5.5V
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Pin Descriptions
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct
multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
Minimum Mode System
The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/MX = V
mode are described; all other pin functions are as described in the following.
SYMBOL
SYMBOL
RESET
MN/MX
TEST
DT/R
GND
INTA
VCC
M/IO
DEN
CLK
NMI
ALE
WR
NUMBER
NUMBER
1, 20
PIN
PIN
23
17
21
19
40
33
28
29
24
25
27
26
(Continued)
5
TYPE
TYPE
O
O
O
O
O
O
I
I
I
I
I
TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,
otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
NON-MASKABLE INTERRUPT: An edge triggered input which causes a type 2 interrupt. A subroutine
is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable
internally by software. A transition from LOW to HIGH initiates the interrupt at the end of the current
instruction. This input is internally synchronized.
RESET: Causes the processor to immediately terminate its present activity. The signal must transition
LOW to HIGH and remain active HIGH for at least 4 clock cycles. It restarts execution, as described
in the “Instruction Set Summary” on page 31 when RESET returns LOW. RESET is internally
synchronized.
CLOCK: Provides the basic timing for the processor and bus controller. It is asymmetric with a 33%
duty cycle to provide optimized internal timing.
VCC: +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 is recommended for
decoupling.
GND: Ground. Note: Both must be connected. A 0.1µF capacitor between pins 1 and 20 is
recommended for decoupling.
MINIMUM/MAXIMUM: Indicates what mode the processor is to operate in. The two modes are
discussed in the following sections.
STATUS LINE: Logically equivalent to S2 in the maximum mode. It is used to distinguish a memory
access from an I/O access. M/lO becomes valid in the t4 preceding a bus cycle and remains valid until
the final t4 of the cycle (M = HIGH, I/O = LOW). M/lO is held to a high impedance logic one during local
bus “hold acknowledge”.
WRITE: Indicates that the processor is performing a write memory or write I/O cycle, depending on
the state of the M/IO signal. WR is active for t2, t3 and tW of any write cycle. It is active LOW, and is
held to high impedance logic one during local bus “hold acknowledge”.
INTERRUPT ACKNOWLEDGE: Used as a read strobe for interrupt acknowledge cycles. It is active
LOW during t2, t3 and tW of each interrupt acknowledge cycle. Note that INTA is never floated.
ADDRESS LATCH ENABLE: Provided by the processor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock LOW of t1 of any bus cycle. Note that ALE is never
floated.
DATA TRANSMIT/RECEIVE: Needed in a minimum system that desires to use a data bus transceiver.
It is used to control the direction of data flow through the transceiver. Logically,
DT/R is equivalent to S1 in maximum mode, and its timing is the same as for M/IO (T = HIGH,
R = LOW). DT/R is held to a high impedance logic one during local bus “hold acknowledge”.
DATA ENABLE: Provided as an output enable for a bus transceiver in a minimum system which uses
the transceiver. DEN is active LOW during each memory and I/O access and for INTA cycles. For a
read or INTA cycle it is active from the middle of t2 until the middle of t4, while for a write cycle it is
active from the beginning of t2 until the middle of t4. DEN is held to a high impedance logic one during
local bus “hold acknowledge”.
80C86
DESCRIPTION
DESCRIPTION
CC
). Only the pin functions which are unique to minimum
January 9, 2009
FN2957.3