MPC8555ECPXAJD Freescale Semiconductor, MPC8555ECPXAJD Datasheet - Page 19

• Manufacturer Part Number: MPC8555ECPXAJD
• Description: IC MPU POWERQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8555ECPXAJD

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8555CDS - BOARD EVALUATION CDS FOR 8555CWH-PPC-8555N-VX - BOARD EVAL QUICCSTART MPC8555CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540CWH-PPC-8555N-VE - EVALUATION SYSTEM QUICC MPC8555E
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor
At recommended operating conditions with GV
MCS(n) output hold with respect to MCK
MCK to MDQS
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control
4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
5. Note that t
6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8555E. Note that t
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
outputs (A) are setup (S) or output valid time. Also, t
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
Register. For the skew measurements referenced for t
address/command valid with the rising edge of MCK.
ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle. The MCSx pins are separated from the ADDR/CMD (address and command) bus in the HW spec. This
was separated because the MCSx pins typically have different loadings than the rest of the address and command bus,
even though they have the same timings.
(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). In the source synchronous mode,
MDQS can launch later than MCK by 0.3 ns at the maximum. However, MCK may launch later than MDQS by as much as
0.9 ns. t
synchronous mode, this typically is set to the same delay as the clock adjust in the CLK_CNTL register. The timing
parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the
MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description and
understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8555E.
conventions described in note 1.
DDKHAS
Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
DDKHMH
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source
follows the symbol conventions described in note 1. For example, t
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
333 MHz
266 MHz
200 MHz
DD
of 2.5 V ± 5%.
Symbol
t
t
t
t
t
t
t
t
DDKHDS,
DDKHDX,
MCK
DDKHMH
DDKHMP
DDKHCX
DDKLME
DDKLDS
DDKLDX
DDKLDX
AOSKEW
memory clock reference (K) goes from the high (H) state until
1
symbolizes DDR timing (DD) for the time t
it is assumed that the clock adjustment is set to align the
–0.5 × t
(first two letters of functional block)(signal)(state) (reference)(state)
for outputs. Output hold time can be read as DDR timing
1200
1200
2.65
–0.9
–1.1
–1.2
–0.9
Min
900
900
900
900
2.0
3.8
MCK
– 0.9
–0.5 × t
DDKHMH
Max
0.3
0.5
0.6
0.3
—
—
—
MCK
describes the DDR timing
DDKHMP
+0.3
MCK
follows the symbol
memory clock
Unit
ns
ns
ps
ps
ns
ns
DDR SDRAM
Notes
4
5
6
6
7
7
for
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